683 lines
20 KiB
C
683 lines
20 KiB
C
/*
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* @copyright (c) 2023-2024, MR Development Team
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*
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* @license SPDX-License-Identifier: Apache-2.0
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*
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* @date 2023-11-01 MacRsh First version
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*/
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#include "include/device/mr_spi.h"
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#ifdef MR_USING_SPI
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#ifdef MR_USING_PIN
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#include "include/device/mr_pin.h"
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#else
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#warning "Please define MR_USING_PIN. Otherwise SPI-CS will not work."
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#endif /* MR_USING_PIN */
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static int mr_spi_bus_open(struct mr_dev *dev)
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{
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struct mr_spi_bus *spi_bus = (struct mr_spi_bus *)dev;
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struct mr_spi_bus_ops *ops = (struct mr_spi_bus_ops *)dev->drv->ops;
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/* Reset the hold */
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spi_bus->hold = MR_FALSE;
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#ifdef MR_USING_PIN
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spi_bus->cs_desc = mr_dev_open("pin", MR_OFLAG_RDWR);
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#endif /* MR_USING_PIN */
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return ops->configure(spi_bus, &spi_bus->config);
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}
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static int mr_spi_bus_close(struct mr_dev *dev)
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{
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struct mr_spi_bus *spi_bus = (struct mr_spi_bus *)dev;
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struct mr_spi_bus_ops *ops = (struct mr_spi_bus_ops *)dev->drv->ops;
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struct mr_spi_config close_config = {0};
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#ifdef MR_USING_PIN
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if (spi_bus->cs_desc >= 0)
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{
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mr_dev_close(spi_bus->cs_desc);
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spi_bus->cs_desc = -1;
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}
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#endif /* MR_USING_PIN */
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return ops->configure(spi_bus, &close_config);
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}
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static ssize_t mr_spi_bus_read(struct mr_dev *dev, int off, void *buf, size_t size, int async)
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{
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return MR_EIO;
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}
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static ssize_t mr_spi_bus_write(struct mr_dev *dev, int off, const void *buf, size_t size, int async)
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{
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return MR_EIO;
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}
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static ssize_t mr_spi_bus_isr(struct mr_dev *dev, int event, void *args)
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{
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struct mr_spi_bus *spi_bus = (struct mr_spi_bus *)dev;
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struct mr_spi_bus_ops *ops = (struct mr_spi_bus_ops *)spi_bus->dev.drv->ops;
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switch (event)
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{
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case MR_ISR_SPI_RD_INT:
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{
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struct mr_spi_dev *spi_dev = (struct mr_spi_dev *)spi_bus->owner;
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uint32_t data = ops->read(spi_bus);
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#ifdef MR_USING_PIN
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/* Check if CS is active */
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if ((spi_dev->cs_active != MR_SPI_CS_ACTIVE_NONE) && (spi_bus->cs_desc >= 0))
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{
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uint8_t level = !spi_dev->cs_active;
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mr_dev_read(spi_bus->cs_desc, &level, sizeof(level));
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if (level != spi_dev->cs_active)
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{
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return MR_EINVAL;
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}
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}
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#endif /* MR_USING_PIN */
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/* Read data to FIFO. if callback is set, call it */
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mr_ringbuf_write_force(&spi_dev->rd_fifo, &data, (spi_bus->config.data_bits >> 3));
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if (spi_dev->dev.rd_call.call != MR_NULL)
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{
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ssize_t size = (ssize_t)mr_ringbuf_get_data_size(&spi_dev->rd_fifo);
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spi_dev->dev.rd_call.call(spi_dev->dev.rd_call.desc, &size);
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}
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return MR_EOK;
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}
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default:
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{
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return MR_ENOTSUP;
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}
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}
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}
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/**
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* @brief This function registers a spi-bus.
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*
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* @param spi_bus The spi-bus.
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* @param name The name of the spi-bus.
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* @param drv The driver of the spi-bus.
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*
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* @return MR_EOK on success, otherwise an error code.
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*/
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int mr_spi_bus_register(struct mr_spi_bus *spi_bus, const char *name, struct mr_drv *drv)
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{
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static struct mr_dev_ops ops =
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{
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mr_spi_bus_open,
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mr_spi_bus_close,
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mr_spi_bus_read,
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mr_spi_bus_write,
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MR_NULL,
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mr_spi_bus_isr
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};
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struct mr_spi_config default_config = MR_SPI_CONFIG_DEFAULT;
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MR_ASSERT(spi_bus != MR_NULL);
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MR_ASSERT(name != MR_NULL);
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MR_ASSERT(drv != MR_NULL);
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MR_ASSERT(drv->ops != MR_NULL);
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/* Initialize the fields */
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spi_bus->config = default_config;
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spi_bus->owner = MR_NULL;
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spi_bus->hold = MR_FALSE;
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spi_bus->cs_desc = -1;
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/* Register the spi-bus */
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return mr_dev_register(&spi_bus->dev, name, Mr_Dev_Type_SPI, MR_SFLAG_RDWR, &ops, drv);
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}
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#ifdef MR_USING_PIN
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static void spi_dev_cs_configure(struct mr_spi_dev *spi_dev, int state)
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{
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struct mr_spi_bus *spi_bus = (struct mr_spi_bus *)spi_dev->dev.parent;
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int desc = spi_bus->cs_desc;
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/* Check the descriptor is valid */
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if (desc < 0)
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{
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return;
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}
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if (spi_dev->cs_active != MR_SPI_CS_ACTIVE_NONE)
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{
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int old_number = -1;
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/* Temporarily store the old number */
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mr_dev_ioctl(desc, MR_CTL_PIN_GET_NUMBER, &old_number);
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/* Set the new number */
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mr_dev_ioctl(desc, MR_CTL_PIN_SET_NUMBER, MR_MAKE_LOCAL(int, spi_dev->cs_pin));
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if (state == MR_ENABLE)
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{
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int mode = MR_PIN_MODE_NONE;
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if (spi_dev->config.host_slave == MR_SPI_HOST)
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{
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mode = MR_PIN_MODE_OUTPUT;
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} else
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{
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if (spi_dev->cs_active == MR_SPI_CS_ACTIVE_LOW)
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{
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mode = MR_PIN_MODE_INPUT_UP;
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} else
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{
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mode = MR_PIN_MODE_INPUT_DOWN;
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}
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}
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mr_dev_ioctl(desc, MR_CTL_PIN_SET_MODE, &mode);
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mr_dev_write(desc, MR_MAKE_LOCAL(uint8_t, !spi_dev->cs_active), sizeof(uint8_t));
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} else
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{
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mr_dev_ioctl(desc, MR_CTL_PIN_SET_MODE, MR_MAKE_LOCAL(int, MR_PIN_MODE_NONE));
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}
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/* Restore the old number */
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mr_dev_ioctl(desc, MR_CTL_PIN_SET_NUMBER, &old_number);
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}
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}
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#endif /* MR_USING_PIN */
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MR_INLINE void spi_dev_cs_set(struct mr_spi_dev *spi_dev, int state)
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{
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struct mr_spi_bus *spi_bus = (struct mr_spi_bus *)spi_dev->dev.parent;
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#ifdef MR_USING_PIN
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if ((spi_dev->cs_active != MR_SPI_CS_ACTIVE_NONE) && (spi_bus->cs_desc >= 0))
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{
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mr_dev_write(spi_bus->cs_desc, MR_MAKE_LOCAL(uint8_t, !(state ^ spi_dev->cs_active)), sizeof(uint8_t));
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}
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#endif /* MR_USING_PIN */
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}
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MR_INLINE int spi_dev_take_bus(struct mr_spi_dev *spi_dev)
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{
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struct mr_spi_bus *spi_bus = (struct mr_spi_bus *)spi_dev->dev.parent;
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struct mr_spi_bus_ops *ops = (struct mr_spi_bus_ops *)spi_bus->dev.drv->ops;
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/* Check if the bus is busy */
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if ((spi_bus->hold == MR_TRUE) && (spi_dev != spi_bus->owner))
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{
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return MR_EBUSY;
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}
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if (spi_dev != spi_bus->owner)
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{
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/* Reconfigure the bus */
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if (spi_dev->config.baud_rate != spi_bus->config.baud_rate
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|| spi_dev->config.host_slave != spi_bus->config.host_slave
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|| spi_dev->config.mode != spi_bus->config.mode
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|| spi_dev->config.data_bits != spi_bus->config.data_bits
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|| spi_dev->config.bit_order != spi_bus->config.bit_order)
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{
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int ret = ops->configure(spi_bus, &spi_dev->config);
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if (ret < 0)
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{
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return ret;
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}
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}
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spi_bus->config = spi_dev->config;
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spi_bus->owner = spi_dev;
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#ifdef MR_USING_PIN
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if (spi_bus->cs_desc >= 0)
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{
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mr_dev_ioctl(spi_bus->cs_desc, MR_CTL_PIN_SET_NUMBER, MR_MAKE_LOCAL(int, spi_dev->cs_pin));
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}
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#endif /* MR_USING_PIN */
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}
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spi_bus->hold = MR_TRUE;
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return MR_EOK;
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}
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MR_INLINE int spi_dev_release_bus(struct mr_spi_dev *spi_dev)
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{
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struct mr_spi_bus *spi_bus = (struct mr_spi_bus *)spi_dev->dev.parent;
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if (spi_dev != spi_bus->owner)
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{
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return MR_EINVAL;
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}
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/* If it is a host, release the bus. The slave needs to hold the bus at all times */
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if (spi_dev->config.host_slave == MR_SPI_HOST)
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{
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spi_bus->hold = MR_FALSE;
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}
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return MR_EOK;
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}
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#define MR_SPI_RD (0)
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#define MR_SPI_WR (1)
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#define MR_SPI_RDWR (2)
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static ssize_t spi_dev_transfer(struct mr_spi_dev *spi_dev, void *rd_buf, const void *wr_buf, size_t size, int rdwr)
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{
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struct mr_spi_bus *spi_bus = (struct mr_spi_bus *)spi_dev->dev.parent;
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struct mr_spi_bus_ops *ops = (struct mr_spi_bus_ops *)spi_bus->dev.drv->ops;
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size_t tf_size;
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if (rdwr == MR_SPI_RD)
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{
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switch (spi_dev->config.data_bits)
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{
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case MR_SPI_DATA_BITS_8:
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{
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uint8_t *rd_data = (uint8_t *)rd_buf;
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MR_BIT_CLR(size, sizeof(*rd_data) - 1);
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for (tf_size = 0; tf_size < size; tf_size += sizeof(*rd_data))
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{
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ops->write(spi_bus, 0);
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*rd_data = ops->read(spi_bus);
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rd_data++;
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}
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break;
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}
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case MR_SPI_DATA_BITS_16:
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{
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uint16_t *rd_data = (uint16_t *)rd_buf;
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MR_BIT_CLR(size, sizeof(*rd_data) - 1);
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for (tf_size = 0; tf_size < size; tf_size += sizeof(*rd_data))
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{
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ops->write(spi_bus, 0);
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*rd_data = ops->read(spi_bus);
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rd_data++;
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}
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break;
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}
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case MR_SPI_DATA_BITS_32:
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{
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uint32_t *rd_data = (uint32_t *)rd_buf;
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MR_BIT_CLR(size, sizeof(*rd_data) - 1);
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for (tf_size = 0; tf_size < size; tf_size += sizeof(*rd_data))
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{
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ops->write(spi_bus, 0);
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*rd_data = ops->read(spi_bus);
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rd_data++;
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}
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break;
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}
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default:
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{
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return MR_EINVAL;
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}
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}
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} else if (rdwr == MR_SPI_WR)
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{
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switch (spi_dev->config.data_bits)
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{
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case MR_SPI_DATA_BITS_8:
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{
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uint8_t *wr_data = (uint8_t *)wr_buf;
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MR_BIT_CLR(size, sizeof(*wr_data) - 1);
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for (tf_size = 0; tf_size < size; tf_size += sizeof(*wr_data))
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{
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ops->write(spi_bus, *wr_data);
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ops->read(spi_bus);
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wr_data++;
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}
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break;
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}
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case MR_SPI_DATA_BITS_16:
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{
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uint16_t *wr_data = (uint16_t *)wr_buf;
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MR_BIT_CLR(size, sizeof(*wr_data) - 1);
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for (tf_size = 0; tf_size < size; tf_size += sizeof(*wr_data))
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{
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ops->write(spi_bus, *wr_data);
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ops->read(spi_bus);
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wr_data++;
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}
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break;
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}
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case MR_SPI_DATA_BITS_32:
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{
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uint32_t *wr_data = (uint32_t *)wr_buf;
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MR_BIT_CLR(size, sizeof(*wr_data) - 1);
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for (tf_size = 0; tf_size < size; tf_size += sizeof(*wr_data))
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{
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ops->write(spi_bus, *wr_data);
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ops->read(spi_bus);
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wr_data++;
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}
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break;
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}
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default:
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{
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return MR_EINVAL;
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}
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}
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} else
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{
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switch (spi_dev->config.data_bits)
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{
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case MR_SPI_DATA_BITS_8:
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{
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uint8_t *rd_data = (uint8_t *)rd_buf;
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uint8_t *wr_data = (uint8_t *)wr_buf;
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MR_BIT_CLR(size, sizeof(*wr_data) - 1);
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for (tf_size = 0; tf_size < size; tf_size += sizeof(*wr_data))
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{
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ops->write(spi_bus, *wr_data);
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*rd_data = ops->read(spi_bus);
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rd_data++;
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wr_data++;
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}
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break;
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}
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case MR_SPI_DATA_BITS_16:
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{
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uint16_t *wr_data = (uint16_t *)wr_buf;
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uint16_t *rd_data = (uint16_t *)rd_buf;
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MR_BIT_CLR(size, sizeof(*wr_data) - 1);
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for (tf_size = 0; tf_size < size; tf_size += sizeof(*wr_data))
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{
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ops->write(spi_bus, *wr_data);
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*rd_data = ops->read(spi_bus);
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rd_data++;
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wr_data++;
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}
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break;
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}
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case MR_SPI_DATA_BITS_32:
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{
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uint32_t *wr_data = (uint32_t *)wr_buf;
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uint32_t *rd_data = (uint32_t *)rd_buf;
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MR_BIT_CLR(size, sizeof(*wr_data) - 1);
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for (tf_size = 0; tf_size < size; tf_size += sizeof(*wr_data))
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{
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ops->write(spi_bus, *wr_data);
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*rd_data = ops->read(spi_bus);
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rd_data++;
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wr_data++;
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}
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break;
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}
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default:
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{
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return MR_EINVAL;
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}
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}
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}
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return (ssize_t)tf_size;
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}
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static int mr_spi_dev_open(struct mr_dev *dev)
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{
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struct mr_spi_dev *spi_dev = (struct mr_spi_dev *)dev;
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#ifdef MR_USING_PIN
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spi_dev_cs_configure(spi_dev, MR_ENABLE);
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#endif /* MR_USING_PIN */
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/* Allocate FIFO buffers */
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return mr_ringbuf_allocate(&spi_dev->rd_fifo, spi_dev->rd_bufsz);
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}
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static int mr_spi_dev_close(struct mr_dev *dev)
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{
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struct mr_spi_dev *spi_dev = (struct mr_spi_dev *)dev;
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#ifdef MR_USING_PIN
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spi_dev_cs_configure(spi_dev, MR_DISABLE);
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#endif /* MR_USING_PIN */
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/* Free FIFO buffers */
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mr_ringbuf_free(&spi_dev->rd_fifo);
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return MR_EOK;
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}
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static ssize_t mr_spi_dev_read(struct mr_dev *dev, int off, void *buf, size_t size, int async)
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{
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struct mr_spi_dev *spi_dev = (struct mr_spi_dev *)dev;
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ssize_t ret = spi_dev_take_bus(spi_dev);
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if (ret < 0)
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{
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return ret;
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}
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if (spi_dev->config.host_slave == MR_SPI_HOST)
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{
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spi_dev_cs_set(spi_dev, MR_ENABLE);
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if (off >= 0)
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{
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/* Send the address of the register that needs to be read */
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spi_dev_transfer(spi_dev, MR_NULL, &off, (spi_dev->config.reg_bits >> 3), MR_SPI_WR);
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}
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ret = spi_dev_transfer(spi_dev, buf, MR_NULL, size, MR_SPI_RD);
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spi_dev_cs_set(spi_dev, MR_DISABLE);
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} else
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{
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if (mr_ringbuf_get_bufsz(&spi_dev->rd_fifo) == 0)
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{
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ret = spi_dev_transfer(spi_dev, buf, MR_NULL, size, MR_SPI_RD);
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} else
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{
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ret = (ssize_t)mr_ringbuf_read(&spi_dev->rd_fifo, buf, size);
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}
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}
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spi_dev_release_bus(spi_dev);
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return ret;
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}
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static ssize_t mr_spi_dev_write(struct mr_dev *dev, int off, const void *buf, size_t size, int async)
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{
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struct mr_spi_dev *spi_dev = (struct mr_spi_dev *)dev;
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ssize_t ret = spi_dev_take_bus(spi_dev);
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if (ret < 0)
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{
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return ret;
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}
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if (spi_dev->config.host_slave == MR_SPI_HOST)
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{
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spi_dev_cs_set(spi_dev, MR_ENABLE);
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if (off >= 0)
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{
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/* Send the address of the register that needs to be written */
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spi_dev_transfer(spi_dev, MR_NULL, &off, (spi_dev->config.reg_bits >> 3), MR_SPI_WR);
|
|
}
|
|
|
|
ret = spi_dev_transfer(spi_dev, MR_NULL, buf, size, MR_SPI_WR);
|
|
spi_dev_cs_set(spi_dev, MR_DISABLE);
|
|
} else
|
|
{
|
|
ret = spi_dev_transfer(spi_dev, MR_NULL, buf, size, MR_SPI_WR);
|
|
}
|
|
|
|
spi_dev_release_bus(spi_dev);
|
|
return ret;
|
|
}
|
|
|
|
static int mr_spi_dev_ioctl(struct mr_dev *dev, int off, int cmd, void *args)
|
|
{
|
|
struct mr_spi_dev *spi_dev = (struct mr_spi_dev *)dev;
|
|
|
|
switch (cmd)
|
|
{
|
|
case MR_CTL_SPI_SET_CONFIG:
|
|
{
|
|
if (args != MR_NULL)
|
|
{
|
|
struct mr_spi_bus *spi_bus = (struct mr_spi_bus *)dev->parent;
|
|
struct mr_spi_config config = *(struct mr_spi_config *)args;
|
|
|
|
#ifdef MR_USING_PIN
|
|
/* Reconfigure CS */
|
|
if (config.host_slave != spi_dev->config.host_slave)
|
|
{
|
|
spi_dev->config = config;
|
|
spi_dev_cs_configure(spi_dev, MR_ENABLE);
|
|
}
|
|
#endif /* MR_USING_PIN */
|
|
|
|
/* If holding the bus, release it */
|
|
if (spi_dev == spi_bus->owner)
|
|
{
|
|
spi_bus->hold = MR_FALSE;
|
|
spi_bus->owner = MR_NULL;
|
|
}
|
|
|
|
/* Update the configuration and try again to get the bus */
|
|
spi_dev->config = config;
|
|
if (config.host_slave == MR_SPI_SLAVE)
|
|
{
|
|
int ret = spi_dev_take_bus(spi_dev);
|
|
if (ret < 0)
|
|
{
|
|
return ret;
|
|
}
|
|
}
|
|
return sizeof(config);
|
|
}
|
|
return MR_EINVAL;
|
|
}
|
|
case MR_CTL_SPI_SET_RD_BUFSZ:
|
|
{
|
|
if (args != MR_NULL)
|
|
{
|
|
size_t bufsz = *(size_t *)args;
|
|
|
|
int ret = mr_ringbuf_allocate(&spi_dev->rd_fifo, bufsz);
|
|
spi_dev->rd_bufsz = 0;
|
|
if (ret < 0)
|
|
{
|
|
return ret;
|
|
}
|
|
spi_dev->rd_bufsz = bufsz;
|
|
return sizeof(bufsz);
|
|
}
|
|
return MR_EINVAL;
|
|
}
|
|
case MR_CTL_SPI_CLR_RD_BUF:
|
|
{
|
|
mr_ringbuf_reset(&spi_dev->rd_fifo);
|
|
return MR_EOK;
|
|
}
|
|
case MR_CTL_SPI_TRANSFER:
|
|
{
|
|
if (args != MR_NULL)
|
|
{
|
|
struct mr_spi_transfer transfer = *(struct mr_spi_transfer *)args;
|
|
|
|
int ret = spi_dev_take_bus(spi_dev);
|
|
if (ret < 0)
|
|
{
|
|
return ret;
|
|
}
|
|
|
|
if (spi_dev->config.host_slave == MR_SPI_HOST)
|
|
{
|
|
spi_dev_cs_set(spi_dev, MR_ENABLE);
|
|
ret = (int)spi_dev_transfer(dev->parent,
|
|
transfer.rd_buf,
|
|
transfer.wr_buf,
|
|
transfer.size,
|
|
MR_SPI_RDWR);
|
|
spi_dev_cs_set(spi_dev, MR_DISABLE);
|
|
} else
|
|
{
|
|
ret = (int)spi_dev_transfer(dev->parent,
|
|
transfer.rd_buf,
|
|
transfer.wr_buf,
|
|
transfer.size,
|
|
MR_SPI_RDWR);
|
|
}
|
|
|
|
spi_dev_release_bus(spi_dev);
|
|
return ret;
|
|
}
|
|
return MR_EINVAL;
|
|
}
|
|
case MR_CTL_SPI_GET_CONFIG:
|
|
{
|
|
if (args != MR_NULL)
|
|
{
|
|
struct mr_spi_config *config = (struct mr_spi_config *)args;
|
|
|
|
*config = spi_dev->config;
|
|
return sizeof(*config);
|
|
}
|
|
return MR_EINVAL;
|
|
}
|
|
case MR_CTL_SPI_GET_RD_BUFSZ:
|
|
{
|
|
if (args != MR_NULL)
|
|
{
|
|
size_t *bufsz = (size_t *)args;
|
|
|
|
*bufsz = spi_dev->rd_bufsz;
|
|
return sizeof(*bufsz);
|
|
}
|
|
return MR_EINVAL;
|
|
}
|
|
case MR_CTL_SPI_GET_RD_DATASZ:
|
|
{
|
|
if (args != MR_NULL)
|
|
{
|
|
size_t *datasz = (size_t *)args;
|
|
|
|
*datasz = mr_ringbuf_get_data_size(&spi_dev->rd_fifo);
|
|
return sizeof(*datasz);
|
|
}
|
|
return MR_EINVAL;
|
|
}
|
|
default:
|
|
{
|
|
return MR_ENOTSUP;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief This function registers a spi-device.
|
|
*
|
|
* @param spi_dev The spi-device.
|
|
* @param name The name of the spi-device.
|
|
* @param cs_pin The cs pin of the spi-device.
|
|
* @param cs_active The cs active level of the spi-device.
|
|
*
|
|
* @return MR_EOK on success, otherwise an error code.
|
|
*/
|
|
int mr_spi_dev_register(struct mr_spi_dev *spi_dev, const char *name, int cs_pin, int cs_active)
|
|
{
|
|
static struct mr_dev_ops ops =
|
|
{
|
|
mr_spi_dev_open,
|
|
mr_spi_dev_close,
|
|
mr_spi_dev_read,
|
|
mr_spi_dev_write,
|
|
mr_spi_dev_ioctl,
|
|
MR_NULL
|
|
};
|
|
struct mr_spi_config default_config = MR_SPI_CONFIG_DEFAULT;
|
|
|
|
MR_ASSERT(spi_dev != MR_NULL);
|
|
MR_ASSERT(name != MR_NULL);
|
|
MR_ASSERT((cs_active >= MR_SPI_CS_ACTIVE_LOW) && (cs_active <= MR_SPI_CS_ACTIVE_NONE));
|
|
|
|
/* Initialize the fields */
|
|
spi_dev->config = default_config;
|
|
mr_ringbuf_init(&spi_dev->rd_fifo, MR_NULL, 0);
|
|
#ifndef MR_CFG_SPI_RD_BUFSZ
|
|
#define MR_CFG_SPI_RD_BUFSZ (0)
|
|
#endif /* MR_CFG_SPI_RD_BUFSZ */
|
|
spi_dev->rd_bufsz = MR_CFG_SPI_RD_BUFSZ;
|
|
spi_dev->cs_pin = cs_pin;
|
|
spi_dev->cs_active = (cs_pin >= 0) ? cs_active : MR_SPI_CS_ACTIVE_NONE;
|
|
|
|
/* Register the spi-device */
|
|
return mr_dev_register(&spi_dev->dev, name, Mr_Dev_Type_SPI, MR_SFLAG_RDWR | MR_SFLAG_NONDRV, &ops, MR_NULL);
|
|
}
|
|
|
|
#endif /* MR_USING_SPI */
|