174 lines
6.2 KiB
C
174 lines
6.2 KiB
C
/*
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* @copyright (c) 2023-2024, MR Development Team
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*
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* @license SPDX-License-Identifier: Apache-2.0
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*
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* @date 2023-11-01 MacRsh First version
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*/
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#ifndef _MR_SPI_H_
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#define _MR_SPI_H_
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#include "include/mr_api.h"
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifdef MR_USING_SPI
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/**
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* @brief SPI host/slave.
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*/
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#define MR_SPI_HOST (0) /**< SPI host */
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#define MR_SPI_SLAVE (1) /**< SPI slave */
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/**
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* @brief SPI mode.
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*/
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#define MR_SPI_MODE_0 (0) /**< CPOL = 0, CPHA = 0 */
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#define MR_SPI_MODE_1 (1) /**< CPOL = 0, CPHA = 1 */
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#define MR_SPI_MODE_2 (2) /**< CPOL = 1, CPHA = 0 */
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#define MR_SPI_MODE_3 (3) /**< CPOL = 1, CPHA = 1 */
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/**
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* @brief SPI data bits.
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*/
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#define MR_SPI_DATA_BITS_8 (8) /**< 8 bits data */
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#define MR_SPI_DATA_BITS_16 (16) /**< 16 bits data */
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#define MR_SPI_DATA_BITS_32 (32) /**< 32 bits data */
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/**
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* @brief SPI bit order.
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*/
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#define MR_SPI_BIT_ORDER_LSB (0) /**< LSB first */
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#define MR_SPI_BIT_ORDER_MSB (1) /**< MSB first */
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/**
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* @brief SPI register bits.
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*/
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#define MR_SPI_REG_BITS_8 (8) /**< 8 bits register */
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#define MR_SPI_REG_BITS_16 (16) /**< 16 bits register */
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#define MR_SPI_REG_BITS_32 (32) /**< 32 bits register */
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/**
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* @brief SPI default configuration.
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*/
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#define MR_SPI_CONFIG_DEFAULT \
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{ \
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3000000, \
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MR_SPI_HOST, \
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MR_SPI_MODE_0, \
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MR_SPI_DATA_BITS_8, \
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MR_SPI_BIT_ORDER_MSB, \
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MR_SPI_REG_BITS_8, \
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}
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/**
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* @brief SPI configuration structure.
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*/
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struct mr_spi_config
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{
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uint32_t baud_rate; /**< Baud rate */
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int host_slave; /**< Host/slave */
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int mode; /**< Mode */
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int data_bits; /**< Data bits */
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int bit_order; /**< Bit order */
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int reg_bits; /**< Register bits */
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};
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/**
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* @brief SPI transfer structure.
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*/
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struct mr_spi_transfer
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{
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void *rd_buf; /**< Read buffer */
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const void *wr_buf; /**< Write buffer */
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size_t size; /**< Transfer size */
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};
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/**
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* @brief SPI control command.
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*/
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#define MR_CTL_SPI_SET_CONFIG MR_CTL_SET_CONFIG /**< Set configuration */
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#define MR_CTL_SPI_SET_REG MR_CTL_SET_OFFSET /**< Set register */
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#define MR_CTL_SPI_SET_RD_BUFSZ MR_CTL_SET_RD_BUFSZ /**< Set read buffer size */
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#define MR_CTL_SPI_CLR_RD_BUF MR_CTL_CLR_RD_BUF /**< Clear read buffer */
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#define MR_CTL_SPI_SET_RD_CALL MR_CTL_SET_RD_CALL /**< Set read callback */
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#define MR_CTL_SPI_TRANSFER (0x01) /**< Transfer */
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#define MR_CTL_SPI_GET_CONFIG MR_CTL_GET_CONFIG /**< Get configuration */
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#define MR_CTL_SPI_GET_REG MR_CTL_GET_OFFSET /**< Get register */
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#define MR_CTL_SPI_GET_RD_BUFSZ MR_CTL_GET_RD_BUFSZ /**< Get read buffer size */
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#define MR_CTL_SPI_GET_RD_DATASZ MR_CTL_GET_RD_DATASZ /**< Get read data size */
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#define MR_CTL_SPI_GET_RD_CALL MR_CTL_GET_RD_CALL /**< Get read callback */
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/**
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* @brief SPI data type.
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*/
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typedef uint8_t mr_spi_data_t; /**< SPI read/write data type */
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/**
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* @brief SPI ISR events.
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*/
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#define MR_ISR_SPI_RD_INT (MR_ISR_RD | (0x01 << 8)) /**< Read interrupt */
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/**
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* @brief SPI bus structure.
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*/
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struct mr_spi_bus
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{
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struct mr_dev dev; /**< Device */
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struct mr_spi_config config; /**< Configuration */
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volatile void *owner; /**< Owner */
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volatile int hold; /**< Owner hold */
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int cs_desc; /**< CS descriptor */
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};
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/**
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* @brief SPI bus operations structure.
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*/
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struct mr_spi_bus_ops
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{
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int (*configure)(struct mr_spi_bus *spi_bus, struct mr_spi_config *config);
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uint32_t (*read)(struct mr_spi_bus *spi_bus);
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void (*write)(struct mr_spi_bus *spi_bus, uint32_t data);
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};
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/**
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* @brief SPI CS active level.
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*/
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#define MR_SPI_CS_ACTIVE_LOW (0) /**< Active low */
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#define MR_SPI_CS_ACTIVE_HIGH (1) /**< Active high */
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#define MR_SPI_CS_ACTIVE_NONE (2) /**< No active */
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/**
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* @brief SPI device structure.
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*/
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struct mr_spi_dev
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{
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struct mr_dev dev; /**< Device */
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struct mr_spi_config config; /**< Config */
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struct mr_ringbuf rd_fifo; /**< Read FIFO */
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size_t rd_bufsz; /**< Read buffer size */
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uint32_t cs_pin: 30; /**< CS pin */
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uint32_t cs_active: 2; /**< CS active level */
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};
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/**
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* @addtogroup SPI.
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* @{
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*/
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int mr_spi_bus_register(struct mr_spi_bus *spi_bus, const char *name, struct mr_drv *drv);
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int mr_spi_dev_register(struct mr_spi_dev *spi_dev, const char *name, int cs_pin, int cs_active);
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/** @} */
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#endif /* MR_USING_SPI */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* _MR_SPI_H_ */
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