diff --git a/bsp/st/driver/drv_dac.c b/bsp/st/driver/drv_dac.c new file mode 100644 index 0000000..3d20add --- /dev/null +++ b/bsp/st/driver/drv_dac.c @@ -0,0 +1,163 @@ +/* + * @copyright (c) 2023-2024, MR Development Team + * + * @license SPDX-License-Identifier: Apache-2.0 + * + * @date 2024-01-22 MacRsh First version + */ + +#include "drv_dac.h" + +enum drv_dac_index +{ +#ifdef MR_USING_DAC1 + DRV_INDEX_DAC1, +#endif /* MR_USING_DAC1 */ +#ifdef MR_USING_DAC2 + DRV_INDEX_DAC2, +#endif /* MR_USING_DAC2 */ +#ifdef MR_USING_DAC3 + DRV_INDEX_DAC3, +#endif /* MR_USING_DAC3 */ + DRV_INDEX_DAC_MAX +}; + +static const char *dac_name[] = + { +#ifdef MR_USING_DAC1 + "dac1", +#endif /* MR_USING_DAC1 */ +#ifdef MR_USING_DAC2 + "dac2", +#endif /* MR_USING_DAC2 */ +#ifdef MR_USING_DAC3 + "dac3", +#endif /* MR_USING_DAC3 */ + }; + +static struct drv_dac_data dac_drv_data[] = + { +#ifdef MR_USING_DAC1 + {{0}, DAC1}, +#endif /* MR_USING_DAC1 */ +#ifdef MR_USING_DAC2 + {{0}, DAC2}, +#endif /* MR_USING_DAC2 */ +#ifdef MR_USING_DAC3 + {{0}, DAC3}, +#endif /* MR_USING_DAC3 */ + }; + +static struct drv_dac_channel_data dac_channel_drv_data[] = DRV_DAC_CHANNEL_CONFIG; + +static struct mr_dac dac_dev[MR_ARRAY_NUM(dac_drv_data)]; + +static struct drv_dac_channel_data *drv_dac_get_channel_data(int channel) +{ + if (channel >= MR_ARRAY_NUM(dac_channel_drv_data)) + { + return NULL; + } + return &dac_channel_drv_data[channel]; +} + +static int drv_dac_configure(struct mr_dac *dac, int state) +{ + struct drv_dac_data *dac_data = (struct drv_dac_data *)dac->dev.drv->data; + dac_data->handle.Instance = dac_data->instance; + + if (state == ENABLE) + { + /* Configure DAC */ + HAL_DAC_Init(&dac_data->handle); + } else + { + /* Configure DAC */ + HAL_DAC_DeInit(&dac_data->handle); + } + return MR_EOK; +} + +static int drv_dac_channel_configure(struct mr_dac *dac, int channel, int state) +{ + struct drv_dac_data *dac_data = (struct drv_dac_data *)dac->dev.drv->data; + struct drv_dac_channel_data *dac_channel_data = drv_dac_get_channel_data(channel); + DAC_ChannelConfTypeDef sConfig = {0}; + + /* Check channel is valid */ + if (dac_channel_data == NULL) + { + return MR_EINVAL; + } + + /* Configure Channel */ + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; + HAL_DAC_ConfigChannel(&dac_data->handle, &sConfig, dac_channel_data->channel); + if (state == ENABLE) + { + HAL_DAC_SetValue(&dac_data->handle, dac_channel_data->channel, DAC_ALIGN_12B_R, 0); + HAL_DAC_Start(&dac_data->handle, dac_channel_data->channel); + } else + { + HAL_DAC_Stop(&dac_data->handle, dac_channel_data->channel); + } + return MR_EOK; +} + +static void drv_dac_write(struct mr_dac *dac, int channel, uint32_t data) +{ + struct drv_dac_data *dac_data = (struct drv_dac_data *)dac->dev.drv->data; + struct drv_dac_channel_data *dac_channel_data = drv_dac_get_channel_data(channel); + + /* Check channel is valid */ + if (dac_channel_data == NULL) + { + return; + } + + /* Write data */ + HAL_DAC_SetValue(&dac_data->handle, dac_channel_data->channel, DAC_ALIGN_12B_R, (data & 0xFFF)); +} + +static struct mr_dac_ops dac_drv_ops = + { + drv_dac_configure, + drv_dac_channel_configure, + drv_dac_write, + }; + +static struct mr_drv dac_drv[] = + { +#ifdef MR_USING_DAC1 + { + Mr_Drv_Type_DAC, + &dac_drv_ops, + &dac_drv_data[DRV_INDEX_DAC1], + }, +#endif /* MR_USING_DAC1 */ +#ifdef MR_USING_DAC2 + { + Mr_Drv_Type_DAC, + &dac_drv_ops, + &dac_drv_data[DRV_INDEX_DAC2], + } +#endif /* MR_USING_DAC2 */ +#ifdef MR_USING_DAC3 + { + Mr_Drv_Type_DAC, + &dac_drv_ops, + &dac_drv_data[DRV_INDEX_DAC3], + } +#endif /* MR_USING_DAC3 */ + }; + +int drv_dac_init(void) +{ + for (size_t i = 0; i < MR_ARRAY_NUM(dac_dev); i++) + { + mr_dac_register(&dac_dev[i], dac_name[i], &dac_drv[i]); + } + return MR_EOK; +} +MR_INIT_DRV_EXPORT(drv_dac_init); diff --git a/bsp/st/driver/drv_dac.h b/bsp/st/driver/drv_dac.h new file mode 100644 index 0000000..8710d27 --- /dev/null +++ b/bsp/st/driver/drv_dac.h @@ -0,0 +1,30 @@ +/* + * @copyright (c) 2023-2024, MR Development Team + * + * @license SPDX-License-Identifier: Apache-2.0 + * + * @date 2024-01-22 MacRsh First version + */ + +#ifndef _DRV_DAC_H_ +#define _DRV_DAC_H_ + +#include "include/device/mr_dac.h" +#include "mr_board.h" + +#ifdef MR_USING_DAC + +struct drv_dac_data +{ + DAC_HandleTypeDef handle; + DAC_TypeDef *instance; +}; + +struct drv_dac_channel_data +{ + uint32_t channel; +}; + +#endif /* MR_USING_DAC */ + +#endif /* _DRV_DAC_H_ */ diff --git a/bsp/st/stm32f103/driver/Kconfig b/bsp/st/stm32f103/driver/Kconfig index 340beac..4340fea 100644 --- a/bsp/st/stm32f103/driver/Kconfig +++ b/bsp/st/stm32f103/driver/Kconfig @@ -14,6 +14,12 @@ menu "Driver configure" default n endmenu + menu "DAC" + config MR_USING_DAC1 + bool "Enable DAC1 driver" + default n + endmenu + menu "PWM" config MR_USING_PWM1 bool "Enable PWM1 driver" diff --git a/bsp/st/stm32f103/driver/mr_board.h b/bsp/st/stm32f103/driver/mr_board.h index a5b9209..d0734ad 100644 --- a/bsp/st/stm32f103/driver/mr_board.h +++ b/bsp/st/stm32f103/driver/mr_board.h @@ -15,26 +15,33 @@ extern "C" { #include "stm32f1xx.h" -#define DRV_ADC_CHANNEL_CONFIG \ - { \ - {ADC_CHANNEL_0}, \ - {ADC_CHANNEL_1}, \ - {ADC_CHANNEL_2}, \ - {ADC_CHANNEL_3}, \ - {ADC_CHANNEL_4}, \ - {ADC_CHANNEL_5}, \ - {ADC_CHANNEL_6}, \ - {ADC_CHANNEL_7}, \ - {ADC_CHANNEL_8}, \ - {ADC_CHANNEL_9}, \ - {ADC_CHANNEL_10}, \ - {ADC_CHANNEL_11}, \ - {ADC_CHANNEL_12}, \ - {ADC_CHANNEL_13}, \ - {ADC_CHANNEL_14}, \ - {ADC_CHANNEL_15}, \ - {ADC_CHANNEL_16}, \ - {ADC_CHANNEL_17}, \ +#define DRV_ADC_CHANNEL_CONFIG \ + { \ + {ADC_CHANNEL_0}, \ + {ADC_CHANNEL_1}, \ + {ADC_CHANNEL_2}, \ + {ADC_CHANNEL_3}, \ + {ADC_CHANNEL_4}, \ + {ADC_CHANNEL_5}, \ + {ADC_CHANNEL_6}, \ + {ADC_CHANNEL_7}, \ + {ADC_CHANNEL_8}, \ + {ADC_CHANNEL_9}, \ + {ADC_CHANNEL_10}, \ + {ADC_CHANNEL_11}, \ + {ADC_CHANNEL_12}, \ + {ADC_CHANNEL_13}, \ + {ADC_CHANNEL_14}, \ + {ADC_CHANNEL_15}, \ + {ADC_CHANNEL_16}, \ + {ADC_CHANNEL_17}, \ + } + +#define DRV_DAC_CHANNEL_CONFIG \ + { \ + {NULL}, \ + {DAC_CHANNEL_1}, \ + {DAC_CHANNEL_2}, \ } #define DRV_PIN_IRQ_MAP_CONFIG \ diff --git a/bsp/st/stm32f407/driver/Kconfig b/bsp/st/stm32f407/driver/Kconfig index 5eb0dcd..551a736 100644 --- a/bsp/st/stm32f407/driver/Kconfig +++ b/bsp/st/stm32f407/driver/Kconfig @@ -14,6 +14,12 @@ menu "Driver configure" default n endmenu + menu "DAC" + config MR_USING_DAC1 + bool "Enable DAC1 driver" + default n + endmenu + menu "PWM" config MR_USING_PWM1 bool "Enable PWM1 driver" diff --git a/bsp/st/stm32f407/driver/mr_board.h b/bsp/st/stm32f407/driver/mr_board.h index f941fb6..34c6101 100644 --- a/bsp/st/stm32f407/driver/mr_board.h +++ b/bsp/st/stm32f407/driver/mr_board.h @@ -15,26 +15,33 @@ extern "C" { #include "stm32f4xx.h" -#define DRV_ADC_CHANNEL_CONFIG \ - { \ - {ADC_CHANNEL_0}, \ - {ADC_CHANNEL_1}, \ - {ADC_CHANNEL_2}, \ - {ADC_CHANNEL_3}, \ - {ADC_CHANNEL_4}, \ - {ADC_CHANNEL_5}, \ - {ADC_CHANNEL_6}, \ - {ADC_CHANNEL_7}, \ - {ADC_CHANNEL_8}, \ - {ADC_CHANNEL_9}, \ - {ADC_CHANNEL_10}, \ - {ADC_CHANNEL_11}, \ - {ADC_CHANNEL_12}, \ - {ADC_CHANNEL_13}, \ - {ADC_CHANNEL_14}, \ - {ADC_CHANNEL_15}, \ - {ADC_CHANNEL_16}, \ - {ADC_CHANNEL_17}, \ +#define DRV_ADC_CHANNEL_CONFIG \ + { \ + {ADC_CHANNEL_0}, \ + {ADC_CHANNEL_1}, \ + {ADC_CHANNEL_2}, \ + {ADC_CHANNEL_3}, \ + {ADC_CHANNEL_4}, \ + {ADC_CHANNEL_5}, \ + {ADC_CHANNEL_6}, \ + {ADC_CHANNEL_7}, \ + {ADC_CHANNEL_8}, \ + {ADC_CHANNEL_9}, \ + {ADC_CHANNEL_10}, \ + {ADC_CHANNEL_11}, \ + {ADC_CHANNEL_12}, \ + {ADC_CHANNEL_13}, \ + {ADC_CHANNEL_14}, \ + {ADC_CHANNEL_15}, \ + {ADC_CHANNEL_16}, \ + {ADC_CHANNEL_17}, \ + } + +#define DRV_DAC_CHANNEL_CONFIG \ + { \ + {NULL}, \ + {DAC_CHANNEL_1}, \ + {DAC_CHANNEL_2}, \ } #define DRV_PIN_IRQ_MAP_CONFIG \ diff --git a/bsp/st/stm32f411/driver/mr_board.h b/bsp/st/stm32f411/driver/mr_board.h index f772561..9779922 100644 --- a/bsp/st/stm32f411/driver/mr_board.h +++ b/bsp/st/stm32f411/driver/mr_board.h @@ -15,26 +15,26 @@ extern "C" { #include "stm32f4xx.h" -#define DRV_ADC_CHANNEL_CONFIG \ - { \ - {ADC_CHANNEL_0}, \ - {ADC_CHANNEL_1}, \ - {ADC_CHANNEL_2}, \ - {ADC_CHANNEL_3}, \ - {ADC_CHANNEL_4}, \ - {ADC_CHANNEL_5}, \ - {ADC_CHANNEL_6}, \ - {ADC_CHANNEL_7}, \ - {ADC_CHANNEL_8}, \ - {ADC_CHANNEL_9}, \ - {ADC_CHANNEL_10}, \ - {ADC_CHANNEL_11}, \ - {ADC_CHANNEL_12}, \ - {ADC_CHANNEL_13}, \ - {ADC_CHANNEL_14}, \ - {ADC_CHANNEL_15}, \ - {ADC_CHANNEL_16}, \ - {ADC_CHANNEL_17}, \ +#define DRV_ADC_CHANNEL_CONFIG \ + { \ + {ADC_CHANNEL_0}, \ + {ADC_CHANNEL_1}, \ + {ADC_CHANNEL_2}, \ + {ADC_CHANNEL_3}, \ + {ADC_CHANNEL_4}, \ + {ADC_CHANNEL_5}, \ + {ADC_CHANNEL_6}, \ + {ADC_CHANNEL_7}, \ + {ADC_CHANNEL_8}, \ + {ADC_CHANNEL_9}, \ + {ADC_CHANNEL_10}, \ + {ADC_CHANNEL_11}, \ + {ADC_CHANNEL_12}, \ + {ADC_CHANNEL_13}, \ + {ADC_CHANNEL_14}, \ + {ADC_CHANNEL_15}, \ + {ADC_CHANNEL_16}, \ + {ADC_CHANNEL_17}, \ } #define DRV_PIN_IRQ_MAP_CONFIG \