1.驱动新增使能设备但未使能驱动警告提示。
This commit is contained in:
@@ -10,6 +10,10 @@
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#ifdef MR_USING_ADC
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#ifdef MR_USING_ADC
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#if !defined(MR_USING_ADC1) && !defined(MR_USING_ADC2) && !defined(MR_USING_ADC3)
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#warning "Please enable at least one ADC driver"
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#endif /* !defined(MR_USING_ADC1) && !defined(MR_USING_ADC2) && !defined(MR_USING_ADC3) */
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enum drv_adc_index
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enum drv_adc_index
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{
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{
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#ifdef MR_USING_ADC1
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#ifdef MR_USING_ADC1
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@@ -24,7 +28,7 @@ enum drv_adc_index
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DRV_INDEX_ADC_MAX
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DRV_INDEX_ADC_MAX
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};
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};
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static const char *adc_name[] =
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static const char *adc_path[] =
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{
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{
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#ifdef MR_USING_ADC1
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#ifdef MR_USING_ADC1
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"adc1",
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"adc1",
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@@ -153,34 +157,30 @@ static struct mr_drv adc_drv[] =
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{
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{
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#ifdef MR_USING_ADC1
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#ifdef MR_USING_ADC1
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{
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{
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Mr_Drv_Type_ADC,
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&adc_drv_ops,
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&adc_drv_ops,
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&adc_drv_data[DRV_INDEX_ADC1],
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&adc_drv_data[DRV_INDEX_ADC1],
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},
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},
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#endif /* MR_USING_ADC1 */
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#endif /* MR_USING_ADC1 */
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#ifdef MR_USING_ADC2
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#ifdef MR_USING_ADC2
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{
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{
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Mr_Drv_Type_ADC,
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&adc_drv_ops,
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&adc_drv_ops,
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&adc_drv_data[DRV_INDEX_ADC2],
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&adc_drv_data[DRV_INDEX_ADC2],
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},
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},
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#endif /* MR_USING_ADC2 */
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#endif /* MR_USING_ADC2 */
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#ifdef MR_USING_ADC3
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#ifdef MR_USING_ADC3
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{
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{
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Mr_Drv_Type_ADC,
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&adc_drv_ops,
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&adc_drv_ops,
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&adc_drv_data[DRV_INDEX_ADC3],
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&adc_drv_data[DRV_INDEX_ADC3],
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},
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},
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#endif /* MR_USING_ADC3 */
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#endif /* MR_USING_ADC3 */
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};
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};
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int drv_adc_init(void)
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static void drv_adc_init(void)
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{
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{
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for (size_t i = 0; i < MR_ARRAY_NUM(adc_dev); i++)
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for (size_t i = 0; i < MR_ARRAY_NUM(adc_dev); i++)
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{
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{
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mr_adc_register(&adc_dev[i], adc_name[i], &adc_drv[i]);
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mr_adc_register(&adc_dev[i], adc_path[i], &adc_drv[i]);
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}
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}
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return MR_EOK;
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}
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}
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MR_INIT_DRV_EXPORT(drv_adc_init);
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MR_INIT_DRV_EXPORT(drv_adc_init);
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@@ -8,6 +8,12 @@
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#include "drv_dac.h"
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#include "drv_dac.h"
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#ifdef MR_USING_DAC
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#if !defined(MR_USING_DAC1) && !defined(MR_USING_DAC2) && !defined(MR_USING_DAC3)
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#warning "Please enable at least one DAC driver"
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#endif /* !defined(MR_USING_DAC1) && !defined(MR_USING_DAC2) && !defined(MR_USING_DAC3) */
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enum drv_dac_index
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enum drv_dac_index
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{
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{
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#ifdef MR_USING_DAC1
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#ifdef MR_USING_DAC1
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@@ -131,33 +137,34 @@ static struct mr_drv dac_drv[] =
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{
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{
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#ifdef MR_USING_DAC1
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#ifdef MR_USING_DAC1
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{
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{
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Mr_Drv_Type_DAC,
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MR_DRV_TYPE_DAC,
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&dac_drv_ops,
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&dac_drv_ops,
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&dac_drv_data[DRV_INDEX_DAC1],
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&dac_drv_data[DRV_INDEX_DAC1],
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},
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},
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#endif /* MR_USING_DAC1 */
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#endif /* MR_USING_DAC1 */
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#ifdef MR_USING_DAC2
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#ifdef MR_USING_DAC2
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{
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{
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Mr_Drv_Type_DAC,
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MR_DRV_TYPE_DAC,
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&dac_drv_ops,
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&dac_drv_ops,
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&dac_drv_data[DRV_INDEX_DAC2],
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&dac_drv_data[DRV_INDEX_DAC2],
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}
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}
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#endif /* MR_USING_DAC2 */
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#endif /* MR_USING_DAC2 */
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#ifdef MR_USING_DAC3
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#ifdef MR_USING_DAC3
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{
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{
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Mr_Drv_Type_DAC,
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MR_DRV_TYPE_DAC,
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&dac_drv_ops,
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&dac_drv_ops,
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&dac_drv_data[DRV_INDEX_DAC3],
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&dac_drv_data[DRV_INDEX_DAC3],
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}
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}
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#endif /* MR_USING_DAC3 */
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#endif /* MR_USING_DAC3 */
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};
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};
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int drv_dac_init(void)
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static void drv_dac_init(void)
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{
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{
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for (size_t i = 0; i < MR_ARRAY_NUM(dac_dev); i++)
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for (size_t i = 0; i < MR_ARRAY_NUM(dac_dev); i++)
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{
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{
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mr_dac_register(&dac_dev[i], dac_name[i], &dac_drv[i]);
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mr_dac_register(&dac_dev[i], dac_name[i], &dac_drv[i]);
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}
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}
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return MR_EOK;
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}
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}
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MR_INIT_DRV_EXPORT(drv_dac_init);
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MR_INIT_DRV_EXPORT(drv_dac_init);
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#endif /* MR_USING_DAC */
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@@ -41,20 +41,24 @@ static struct mr_pin pin_dev;
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static struct drv_pin_port_data *drv_pin_get_port_data(int pin)
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static struct drv_pin_port_data *drv_pin_get_port_data(int pin)
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{
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{
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pin >>= 4;
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pin >>= 4;
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#ifdef MR_USING_PIN_CHECK
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if ((pin >= MR_ARRAY_NUM(pin_port_drv_data)) || (pin_port_drv_data[pin].port == MR_NULL))
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if ((pin >= MR_ARRAY_NUM(pin_port_drv_data)) || (pin_port_drv_data[pin].port == MR_NULL))
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{
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{
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return MR_NULL;
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return MR_NULL;
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}
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}
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#endif /* MR_USING_PIN_CHECK */
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return &pin_port_drv_data[pin];
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return &pin_port_drv_data[pin];
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}
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}
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static struct drv_pin_data *drv_pin_get_data(int pin)
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static struct drv_pin_data *drv_pin_get_data(int pin)
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{
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{
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pin &= 0x0f;
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pin &= 0x0f;
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#ifdef MR_USING_PIN_CHECK
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if (pin >= MR_ARRAY_NUM(pin_drv_data))
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if (pin >= MR_ARRAY_NUM(pin_drv_data))
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{
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{
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return MR_NULL;
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return MR_NULL;
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}
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}
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#endif /* MR_USING_PIN_CHECK */
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return &pin_drv_data[pin];
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return &pin_drv_data[pin];
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}
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}
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@@ -215,11 +219,13 @@ static uint8_t drv_pin_read(struct mr_pin *pin, int number)
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struct drv_pin_port_data *pin_port_data = drv_pin_get_port_data(number);
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struct drv_pin_port_data *pin_port_data = drv_pin_get_port_data(number);
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struct drv_pin_data *pin_data = drv_pin_get_data(number);
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struct drv_pin_data *pin_data = drv_pin_get_data(number);
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#ifdef MR_USING_PIN_CHECK
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/* Check pin is valid */
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/* Check pin is valid */
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if (pin_port_data == NULL || pin_data == NULL)
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if (pin_port_data == NULL || pin_data == NULL)
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{
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{
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return 0;
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return 0;
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}
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}
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#endif /* MR_USING_PIN_CHECK */
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return (int)HAL_GPIO_ReadPin(pin_port_data->port, pin_data->pin);
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return (int)HAL_GPIO_ReadPin(pin_port_data->port, pin_data->pin);
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}
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}
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@@ -228,11 +234,13 @@ static void drv_pin_write(struct mr_pin *pin, int number, uint8_t value)
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struct drv_pin_port_data *pin_port_data = drv_pin_get_port_data(number);
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struct drv_pin_port_data *pin_port_data = drv_pin_get_port_data(number);
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struct drv_pin_data *pin_data = drv_pin_get_data(number);
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struct drv_pin_data *pin_data = drv_pin_get_data(number);
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#ifdef MR_USING_PIN_CHECK
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/* Check pin is valid */
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/* Check pin is valid */
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if (pin_port_data == NULL || pin_data == NULL)
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if (pin_port_data == NULL || pin_data == NULL)
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{
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{
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return;
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return;
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}
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}
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#endif /* MR_USING_PIN_CHECK */
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HAL_GPIO_WritePin(pin_port_data->port, pin_data->pin, (GPIO_PinState)value);
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HAL_GPIO_WritePin(pin_port_data->port, pin_data->pin, (GPIO_PinState)value);
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}
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}
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@@ -353,14 +361,13 @@ static struct mr_pin_ops pin_drv_ops =
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static struct mr_drv pin_drv =
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static struct mr_drv pin_drv =
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{
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{
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Mr_Drv_Type_Pin,
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&pin_drv_ops,
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&pin_drv_ops,
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MR_NULL
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MR_NULL
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};
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};
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int drv_pin_init(void)
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static void drv_pin_init(void)
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{
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{
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return mr_pin_register(&pin_dev, "pin", &pin_drv);
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mr_pin_register(&pin_dev, "pin", &pin_drv);
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}
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}
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MR_INIT_DRV_EXPORT(drv_pin_init);
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MR_INIT_DRV_EXPORT(drv_pin_init);
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@@ -10,6 +10,14 @@
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#ifdef MR_USING_PWM
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#ifdef MR_USING_PWM
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#if !defined(MR_USING_PWM1) && !defined(MR_USING_PWM2) && !defined(MR_USING_PWM3) && !defined(MR_USING_PWM4) && \
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!defined(MR_USING_PWM5) && !defined(MR_USING_PWM8) && !defined(MR_USING_PWM9) && !defined(MR_USING_PWM10) && \
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!defined(MR_USING_PWM11) && !defined(MR_USING_PWM12) && !defined(MR_USING_PWM13) && !defined(MR_USING_PWM14)
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#warning "Please enable at least one PWM driver"
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#endif /* !defined(MR_USING_PWM1) && !defined(MR_USING_PWM2) && !defined(MR_USING_PWM3) && !defined(MR_USING_PWM4) && \
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* !defined(MR_USING_PWM5) && !defined(MR_USING_PWM8) && !defined(MR_USING_PWM9) && !defined(MR_USING_PWM10) && \
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* !defined(MR_USING_PWM11) && !defined(MR_USING_PWM12) && !defined(MR_USING_PWM13) && !defined(MR_USING_PWM14) */
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enum drv_pwm_index
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enum drv_pwm_index
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{
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{
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#ifdef MR_USING_PWM1
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#ifdef MR_USING_PWM1
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@@ -57,7 +65,7 @@ enum drv_pwm_index
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DRV_INDEX_PWM_MAX
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DRV_INDEX_PWM_MAX
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};
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};
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static const char *pwm_name[] =
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static const char *pwm_path[] =
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{
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{
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#ifdef MR_USING_PWM1
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#ifdef MR_USING_PWM1
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"pwm1",
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"pwm1",
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@@ -130,7 +138,7 @@ static struct drv_pwm_data pwm_drv_data[] =
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{{0}, TIM8},
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{{0}, TIM8},
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#endif /* MR_USING_PWM8 */
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#endif /* MR_USING_PWM8 */
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#ifdef MR_USING_PWM9
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#ifdef MR_USING_PWM9
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{{0}, TIM8},
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{{0}, TIM9},
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#endif /* MR_USING_PWM9 */
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#endif /* MR_USING_PWM9 */
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#ifdef MR_USING_PWM10
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#ifdef MR_USING_PWM10
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{{0}, TIM10},
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{{0}, TIM10},
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@@ -318,111 +326,96 @@ static struct mr_drv pwm_drv[] =
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{
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{
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#ifdef MR_USING_PWM1
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#ifdef MR_USING_PWM1
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM1]
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&pwm_drv_data[DRV_INDEX_PWM1]
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},
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},
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#endif /* MR_USING_PWM1 */
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#endif /* MR_USING_PWM1 */
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#ifdef MR_USING_PWM2
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#ifdef MR_USING_PWM2
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM2]
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&pwm_drv_data[DRV_INDEX_PWM2]
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},
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},
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#endif /* MR_USING_PWM2 */
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#endif /* MR_USING_PWM2 */
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#ifdef MR_USING_PWM3
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#ifdef MR_USING_PWM3
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM3]
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&pwm_drv_data[DRV_INDEX_PWM3]
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},
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},
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#endif /* MR_USING_PWM3 */
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#endif /* MR_USING_PWM3 */
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#ifdef MR_USING_PWM4
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#ifdef MR_USING_PWM4
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM4]
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&pwm_drv_data[DRV_INDEX_PWM4]
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},
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},
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#endif /* MR_USING_PWM4 */
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#endif /* MR_USING_PWM4 */
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#ifdef MR_USING_PWM5
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#ifdef MR_USING_PWM5
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM5]
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&pwm_drv_data[DRV_INDEX_PWM5]
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},
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},
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#endif /* MR_USING_PWM5 */
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#endif /* MR_USING_PWM5 */
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#ifdef MR_USING_PWM6
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#ifdef MR_USING_PWM6
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM6]
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&pwm_drv_data[DRV_INDEX_PWM6]
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},
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},
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#endif /* MR_USING_PWM6 */
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#endif /* MR_USING_PWM6 */
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#ifdef MR_USING_PWM7
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#ifdef MR_USING_PWM7
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM7]
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&pwm_drv_data[DRV_INDEX_PWM7]
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},
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},
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#endif /* MR_USING_PWM7 */
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#endif /* MR_USING_PWM7 */
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#ifdef MR_USING_PWM8
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#ifdef MR_USING_PWM8
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM8]
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&pwm_drv_data[DRV_INDEX_PWM8]
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},
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},
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#endif /* MR_USING_PWM8 */
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#endif /* MR_USING_PWM8 */
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#ifdef MR_USING_PWM9
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#ifdef MR_USING_PWM9
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM9]
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&pwm_drv_data[DRV_INDEX_PWM9]
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},
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},
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#endif /* MR_USING_PWM9 */
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#endif /* MR_USING_PWM9 */
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#ifdef MR_USING_PWM10
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#ifdef MR_USING_PWM10
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{
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{
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Mr_Drv_Type_PWM,
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&pwm_drv_ops,
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&pwm_drv_ops,
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&pwm_drv_data[DRV_INDEX_PWM10]
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&pwm_drv_data[DRV_INDEX_PWM10]
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},
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},
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#endif /* MR_USING_PWM10 */
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#endif /* MR_USING_PWM10 */
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#ifdef MR_USING_PWM11
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#ifdef MR_USING_PWM11
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM11]
|
&pwm_drv_data[DRV_INDEX_PWM11]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM11 */
|
#endif /* MR_USING_PWM11 */
|
||||||
#ifdef MR_USING_PWM12
|
#ifdef MR_USING_PWM12
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM12]
|
&pwm_drv_data[DRV_INDEX_PWM12]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM12 */
|
#endif /* MR_USING_PWM12 */
|
||||||
#ifdef MR_USING_PWM13
|
#ifdef MR_USING_PWM13
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM13]
|
&pwm_drv_data[DRV_INDEX_PWM13]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM13 */
|
#endif /* MR_USING_PWM13 */
|
||||||
#ifdef MR_USING_PWM14
|
#ifdef MR_USING_PWM14
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM14]
|
&pwm_drv_data[DRV_INDEX_PWM14]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM14 */
|
#endif /* MR_USING_PWM14 */
|
||||||
};
|
};
|
||||||
|
|
||||||
static int drv_pwm_init(void)
|
static void drv_pwm_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(pwm_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(pwm_dev); i++)
|
||||||
{
|
{
|
||||||
mr_pwm_register(&pwm_dev[i], pwm_name[i], &pwm_drv[i], &pwm_info[i]);
|
mr_pwm_register(&pwm_dev[i], pwm_path[i], &pwm_drv[i], &pwm_info[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_pwm_init);
|
MR_INIT_DRV_EXPORT(drv_pwm_init);
|
||||||
|
|
||||||
|
|||||||
@@ -10,6 +10,12 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_SERIAL
|
#ifdef MR_USING_SERIAL
|
||||||
|
|
||||||
|
#if !defined(MR_USING_UART1) && !defined(MR_USING_UART2) && !defined(MR_USING_UART3) && !defined(MR_USING_UART4) && \
|
||||||
|
!defined(MR_USING_UART5) && !defined(MR_USING_UART6) && !defined(MR_USING_UART7) && !defined(MR_USING_UART8)
|
||||||
|
#warning "Please enable at least one Serial driver"
|
||||||
|
#endif /* !defined(MR_USING_UART1) && !defined(MR_USING_UART2) && !defined(MR_USING_UART3) && !defined(MR_USING_UART4) && \
|
||||||
|
* !defined(MR_USING_UART5) && !defined(MR_USING_UART6) && !defined(MR_USING_UART7) && !defined(MR_USING_UART8) */
|
||||||
|
|
||||||
enum drv_serial_index
|
enum drv_serial_index
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_UART1
|
#ifdef MR_USING_UART1
|
||||||
@@ -39,7 +45,7 @@ enum drv_serial_index
|
|||||||
DRV_INDEX_UART_MAX
|
DRV_INDEX_UART_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *serial_name[] =
|
static const char *serial_path[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_UART1
|
#ifdef MR_USING_UART1
|
||||||
"serial1",
|
"serial1",
|
||||||
@@ -362,69 +368,60 @@ static struct mr_drv serial_drv[] =
|
|||||||
{
|
{
|
||||||
#ifdef MR_USING_UART1
|
#ifdef MR_USING_UART1
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART1]
|
&serial_drv_data[DRV_INDEX_UART1]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART1 */
|
#endif /* MR_USING_UART1 */
|
||||||
#ifdef MR_USING_UART2
|
#ifdef MR_USING_UART2
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART2]
|
&serial_drv_data[DRV_INDEX_UART2]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART2 */
|
#endif /* MR_USING_UART2 */
|
||||||
#ifdef MR_USING_UART3
|
#ifdef MR_USING_UART3
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART3]
|
&serial_drv_data[DRV_INDEX_UART3]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART3 */
|
#endif /* MR_USING_UART3 */
|
||||||
#ifdef MR_USING_UART4
|
#ifdef MR_USING_UART4
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART4]
|
&serial_drv_data[DRV_INDEX_UART4]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART4 */
|
#endif /* MR_USING_UART4 */
|
||||||
#ifdef MR_USING_UART5
|
#ifdef MR_USING_UART5
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART5]
|
&serial_drv_data[DRV_INDEX_UART5]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART5 */
|
#endif /* MR_USING_UART5 */
|
||||||
#ifdef MR_USING_UART6
|
#ifdef MR_USING_UART6
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART6]
|
&serial_drv_data[DRV_INDEX_UART6]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART6 */
|
#endif /* MR_USING_UART6 */
|
||||||
#ifdef MR_USING_UART7
|
#ifdef MR_USING_UART7
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART7]
|
&serial_drv_data[DRV_INDEX_UART7]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART7 */
|
#endif /* MR_USING_UART7 */
|
||||||
#ifdef MR_USING_UART8
|
#ifdef MR_USING_UART8
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART8]
|
&serial_drv_data[DRV_INDEX_UART8]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART8 */
|
#endif /* MR_USING_UART8 */
|
||||||
};
|
};
|
||||||
|
|
||||||
int drv_serial_init(void)
|
static void drv_serial_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(serial_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(serial_dev); i++)
|
||||||
{
|
{
|
||||||
mr_serial_register(&serial_dev[i], serial_name[i], &serial_drv[i]);
|
mr_serial_register(&serial_dev[i], serial_path[i], &serial_drv[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_serial_init);
|
MR_INIT_DRV_EXPORT(drv_serial_init);
|
||||||
|
|
||||||
|
|||||||
@@ -10,6 +10,12 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_SPI
|
#ifdef MR_USING_SPI
|
||||||
|
|
||||||
|
#if !defined(MR_USING_SPI1) && !defined(MR_USING_SPI2) && !defined(MR_USING_SPI3) && !defined(MR_USING_SPI4) && \
|
||||||
|
!defined(MR_USING_SPI5) && !defined(MR_USING_SPI6)
|
||||||
|
#warning "Please enable at least one SPI driver"
|
||||||
|
#endif /* !defined(MR_USING_SPI1) && !defined(MR_USING_SPI2) && !defined(MR_USING_SPI3) && !defined(MR_USING_SPI4) && \
|
||||||
|
* !defined(MR_USING_SPI5) && !defined(MR_USING_SPI6) */
|
||||||
|
|
||||||
enum drv_spi_bus_index
|
enum drv_spi_bus_index
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_SPI1
|
#ifdef MR_USING_SPI1
|
||||||
@@ -33,7 +39,7 @@ enum drv_spi_bus_index
|
|||||||
DRV_INDEX_SPI_MAX
|
DRV_INDEX_SPI_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *spi_bus_name[] =
|
static const char *spi_bus_path[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_SPI1
|
#ifdef MR_USING_SPI1
|
||||||
"spi1",
|
"spi1",
|
||||||
@@ -95,6 +101,8 @@ static int drv_spi_bus_configure(struct mr_spi_bus *spi_bus, struct mr_spi_confi
|
|||||||
pclk = HAL_RCC_GetPCLK1Freq();
|
pclk = HAL_RCC_GetPCLK1Freq();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (state == ENABLE)
|
||||||
|
{
|
||||||
psc = pclk / config->baud_rate;
|
psc = pclk / config->baud_rate;
|
||||||
if (psc >= 256)
|
if (psc >= 256)
|
||||||
{
|
{
|
||||||
@@ -122,18 +130,18 @@ static int drv_spi_bus_configure(struct mr_spi_bus *spi_bus, struct mr_spi_confi
|
|||||||
spi_bus_data->handle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
spi_bus_data->handle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (state == ENABLE)
|
|
||||||
{
|
|
||||||
switch (config->host_slave)
|
switch (config->host_slave)
|
||||||
{
|
{
|
||||||
case MR_SPI_HOST:
|
case MR_SPI_HOST:
|
||||||
{
|
{
|
||||||
spi_bus_data->handle.Init.Mode = SPI_MODE_MASTER;
|
spi_bus_data->handle.Init.Mode = SPI_MODE_MASTER;
|
||||||
|
spi_bus_data->handle.Init.NSS = SPI_NSS_SOFT;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case MR_SPI_SLAVE:
|
case MR_SPI_SLAVE:
|
||||||
{
|
{
|
||||||
spi_bus_data->handle.Init.Mode = SPI_MODE_SLAVE;
|
spi_bus_data->handle.Init.Mode = SPI_MODE_SLAVE;
|
||||||
|
spi_bus_data->handle.Init.NSS = SPI_NSS_HARD_INPUT;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default:
|
default:
|
||||||
@@ -211,7 +219,6 @@ static int drv_spi_bus_configure(struct mr_spi_bus *spi_bus, struct mr_spi_confi
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Configure SPI */
|
/* Configure SPI */
|
||||||
spi_bus_data->handle.Init.NSS = SPI_NSS_SOFT;
|
|
||||||
spi_bus_data->handle.Init.Direction = SPI_DIRECTION_2LINES;
|
spi_bus_data->handle.Init.Direction = SPI_DIRECTION_2LINES;
|
||||||
spi_bus_data->handle.Init.TIMode = SPI_TIMODE_DISABLE;
|
spi_bus_data->handle.Init.TIMode = SPI_TIMODE_DISABLE;
|
||||||
spi_bus_data->handle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
spi_bus_data->handle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||||
@@ -339,55 +346,48 @@ static struct mr_drv spi_bus_drv[] =
|
|||||||
{
|
{
|
||||||
#ifdef MR_USING_SPI1
|
#ifdef MR_USING_SPI1
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_SPI,
|
|
||||||
&spi_bus_drv_ops,
|
&spi_bus_drv_ops,
|
||||||
&spi_bus_drv_data[DRV_INDEX_SPI1],
|
&spi_bus_drv_data[DRV_INDEX_SPI1],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_SPI1 */
|
#endif /* MR_USING_SPI1 */
|
||||||
#ifdef MR_USING_SPI2
|
#ifdef MR_USING_SPI2
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_SPI,
|
|
||||||
&spi_bus_drv_ops,
|
&spi_bus_drv_ops,
|
||||||
&spi_bus_drv_data[DRV_INDEX_SPI2],
|
&spi_bus_drv_data[DRV_INDEX_SPI2],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_SPI2 */
|
#endif /* MR_USING_SPI2 */
|
||||||
#ifdef MR_USING_SPI3
|
#ifdef MR_USING_SPI3
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_SPI,
|
|
||||||
&spi_bus_drv_ops,
|
&spi_bus_drv_ops,
|
||||||
&spi_bus_drv_data[DRV_INDEX_SPI3],
|
&spi_bus_drv_data[DRV_INDEX_SPI3],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_SPI3 */
|
#endif /* MR_USING_SPI3 */
|
||||||
#ifdef MR_USING_SPI4
|
#ifdef MR_USING_SPI4
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_SPI,
|
|
||||||
&spi_bus_drv_ops,
|
&spi_bus_drv_ops,
|
||||||
&spi_bus_drv_data[DRV_INDEX_SPI4],
|
&spi_bus_drv_data[DRV_INDEX_SPI4],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_SPI4 */
|
#endif /* MR_USING_SPI4 */
|
||||||
#ifdef MR_USING_SPI5
|
#ifdef MR_USING_SPI5
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_SPI,
|
|
||||||
&spi_bus_drv_ops,
|
&spi_bus_drv_ops,
|
||||||
&spi_bus_drv_data[DRV_INDEX_SPI5],
|
&spi_bus_drv_data[DRV_INDEX_SPI5],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_SPI5 */
|
#endif /* MR_USING_SPI5 */
|
||||||
#ifdef MR_USING_SPI6
|
#ifdef MR_USING_SPI6
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_SPI,
|
|
||||||
&spi_bus_drv_ops,
|
&spi_bus_drv_ops,
|
||||||
&spi_bus_drv_data[DRV_INDEX_SPI6],
|
&spi_bus_drv_data[DRV_INDEX_SPI6],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_SPI6 */
|
#endif /* MR_USING_SPI6 */
|
||||||
};
|
};
|
||||||
|
|
||||||
int drv_spi_bus_init(void)
|
static void drv_spi_bus_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(spi_bus_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(spi_bus_dev); i++)
|
||||||
{
|
{
|
||||||
mr_spi_bus_register(&spi_bus_dev[i], spi_bus_name[i], &spi_bus_drv[i]);
|
mr_spi_bus_register(&spi_bus_dev[i], spi_bus_path[i], &spi_bus_drv[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_spi_bus_init);
|
MR_INIT_DRV_EXPORT(drv_spi_bus_init);
|
||||||
|
|
||||||
|
|||||||
@@ -10,6 +10,14 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_TIMER
|
#ifdef MR_USING_TIMER
|
||||||
|
|
||||||
|
#if !defined(MR_USING_TIMER1) && !defined(MR_USING_TIMER2) && !defined(MR_USING_TIMER3) && !defined(MR_USING_TIMER4) && \
|
||||||
|
!defined(MR_USING_TIMER5) && !defined(MR_USING_TIMER8) && !defined(MR_USING_TIMER9) && !defined(MR_USING_TIMER10) && \
|
||||||
|
!defined(MR_USING_TIMER11) && !defined(MR_USING_TIMER12) && !defined(MR_USING_TIMER13) && !defined(MR_USING_TIMER14)
|
||||||
|
#warning "Please enable at least one Timer driver"
|
||||||
|
#endif /* !defined(MR_USING_TIMER1) && !defined(MR_USING_TIMER2) && !defined(MR_USING_TIMER3) && !defined(MR_USING_TIMER4) &&
|
||||||
|
* !defined(MR_USING_TIMER5) && !defined(MR_USING_TIMER8) && !defined(MR_USING_TIMER9) && !defined(MR_USING_TIMER10) &&
|
||||||
|
* !defined(MR_USING_TIMER11) && !defined(MR_USING_TIMER12) && !defined(MR_USING_TIMER13) && !defined(MR_USING_TIMER14) */
|
||||||
|
|
||||||
enum drv_timer_index
|
enum drv_timer_index
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_TIMER1
|
#ifdef MR_USING_TIMER1
|
||||||
@@ -57,7 +65,7 @@ enum drv_timer_index
|
|||||||
DRV_INDEX_TIMER_MAX
|
DRV_INDEX_TIMER_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *timer_name[] =
|
static const char *timer_path[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_TIMER1
|
#ifdef MR_USING_TIMER1
|
||||||
"timer1",
|
"timer1",
|
||||||
@@ -394,111 +402,96 @@ static struct mr_drv timer_drv[] =
|
|||||||
{
|
{
|
||||||
#ifdef MR_USING_TIMER1
|
#ifdef MR_USING_TIMER1
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER1]
|
&timer_drv_data[DRV_INDEX_TIMER1]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER1 */
|
#endif /* MR_USING_TIMER1 */
|
||||||
#ifdef MR_USING_TIMER2
|
#ifdef MR_USING_TIMER2
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER2]
|
&timer_drv_data[DRV_INDEX_TIMER2]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER2 */
|
#endif /* MR_USING_TIMER2 */
|
||||||
#ifdef MR_USING_TIMER3
|
#ifdef MR_USING_TIMER3
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER3]
|
&timer_drv_data[DRV_INDEX_TIMER3]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER3 */
|
#endif /* MR_USING_TIMER3 */
|
||||||
#ifdef MR_USING_TIMER4
|
#ifdef MR_USING_TIMER4
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER4]
|
&timer_drv_data[DRV_INDEX_TIMER4]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER4 */
|
#endif /* MR_USING_TIMER4 */
|
||||||
#ifdef MR_USING_TIMER5
|
#ifdef MR_USING_TIMER5
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER5]
|
&timer_drv_data[DRV_INDEX_TIMER5]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER5 */
|
#endif /* MR_USING_TIMER5 */
|
||||||
#ifdef MR_USING_TIMER6
|
#ifdef MR_USING_TIMER6
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER6]
|
&timer_drv_data[DRV_INDEX_TIMER6]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER6 */
|
#endif /* MR_USING_TIMER6 */
|
||||||
#ifdef MR_USING_TIMER7
|
#ifdef MR_USING_TIMER7
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER7]
|
&timer_drv_data[DRV_INDEX_TIMER7]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER7 */
|
#endif /* MR_USING_TIMER7 */
|
||||||
#ifdef MR_USING_TIMER8
|
#ifdef MR_USING_TIMER8
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER8]
|
&timer_drv_data[DRV_INDEX_TIMER8]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER8 */
|
#endif /* MR_USING_TIMER8 */
|
||||||
#ifdef MR_USING_TIMER9
|
#ifdef MR_USING_TIMER9
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER9]
|
&timer_drv_data[DRV_INDEX_TIMER9]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER9 */
|
#endif /* MR_USING_TIMER9 */
|
||||||
#ifdef MR_USING_TIMER10
|
#ifdef MR_USING_TIMER10
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER10]
|
&timer_drv_data[DRV_INDEX_TIMER10]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER10 */
|
#endif /* MR_USING_TIMER10 */
|
||||||
#ifdef MR_USING_TIMER11
|
#ifdef MR_USING_TIMER11
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER11]
|
&timer_drv_data[DRV_INDEX_TIMER11]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER11 */
|
#endif /* MR_USING_TIMER11 */
|
||||||
#ifdef MR_USING_TIMER12
|
#ifdef MR_USING_TIMER12
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER12]
|
&timer_drv_data[DRV_INDEX_TIMER12]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER12 */
|
#endif /* MR_USING_TIMER12 */
|
||||||
#ifdef MR_USING_TIMER13
|
#ifdef MR_USING_TIMER13
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER13]
|
&timer_drv_data[DRV_INDEX_TIMER13]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER13 */
|
#endif /* MR_USING_TIMER13 */
|
||||||
#ifdef MR_USING_TIMER14
|
#ifdef MR_USING_TIMER14
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER14]
|
&timer_drv_data[DRV_INDEX_TIMER14]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER14 */
|
#endif /* MR_USING_TIMER14 */
|
||||||
};
|
};
|
||||||
|
|
||||||
int drv_timer_init(void)
|
static void drv_timer_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(timer_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(timer_dev); i++)
|
||||||
{
|
{
|
||||||
mr_timer_register(&timer_dev[i], timer_name[i], &timer_drv[i], &timer_info[i]);
|
mr_timer_register(&timer_dev[i], timer_path[i], &timer_drv[i], &timer_info[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_timer_init);
|
MR_INIT_DRV_EXPORT(drv_timer_init);
|
||||||
|
|
||||||
|
|||||||
@@ -90,8 +90,11 @@ extern "C" {
|
|||||||
|
|
||||||
#if (MR_CFG_SPI1_GROUP == 1)
|
#if (MR_CFG_SPI1_GROUP == 1)
|
||||||
#define DRV_SPI1_CONFIG \
|
#define DRV_SPI1_CONFIG \
|
||||||
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_5, GPIOC, GPIO_Pin_7, GPIOC, GPIO_Pin_6, SPI1_IRQn, 0}
|
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_1, GPIOC, GPIO_Pin_5, GPIOC, GPIO_Pin_7, GPIOC, GPIO_Pin_6, SPI1_IRQn, 0}
|
||||||
#endif /* MR_CFG_SPI2_GROUP */
|
#elif (MR_CFG_SPI1_GROUP == 2)
|
||||||
|
#define DRV_SPI1_CONFIG \
|
||||||
|
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_0, GPIOC, GPIO_Pin_5, GPIOC, GPIO_Pin_7, GPIOC, GPIO_Pin_6, SPI1_IRQn, GPIO_Remap_SPI1}
|
||||||
|
#endif /* MR_CFG_SPI1_GROUP */
|
||||||
|
|
||||||
#define DRV_TIMER1_CONFIG \
|
#define DRV_TIMER1_CONFIG \
|
||||||
{TIM1, RCC_APB2Periph_TIM1, TIM1_UP_IRQn}
|
{TIM1, RCC_APB2Periph_TIM1, TIM1_UP_IRQn}
|
||||||
|
|||||||
@@ -174,14 +174,14 @@ extern "C" {
|
|||||||
|
|
||||||
#if (MR_CFG_SPI1_GROUP == 1)
|
#if (MR_CFG_SPI1_GROUP == 1)
|
||||||
#define DRV_SPI1_CONFIG \
|
#define DRV_SPI1_CONFIG \
|
||||||
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_5, GPIOA, GPIO_Pin_6, GPIOA, GPIO_Pin_7, SPI1_IRQn, 0}
|
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_4, GPIOA, GPIO_Pin_5, GPIOA, GPIO_Pin_6, GPIOA, GPIO_Pin_7, SPI1_IRQn, 0}
|
||||||
#elif (MR_CFG_SPI1_GROUP == 2)
|
#elif (MR_CFG_SPI1_GROUP == 2)
|
||||||
#define DRV_SPI1_CONFIG \
|
#define DRV_SPI1_CONFIG \
|
||||||
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_3, GPIOB, GPIO_Pin_4, GPIOB, GPIO_Pin_5, SPI1_IRQn, GPIO_Remap_SPI1}
|
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, GPIOA, GPIO_Pin_15, GPIOB, GPIO_Pin_3, GPIOB, GPIO_Pin_4, GPIOB, GPIO_Pin_5, SPI1_IRQn, GPIO_Remap_SPI1}
|
||||||
#endif /* MR_CFG_SPI1_GROUP */
|
#endif /* MR_CFG_SPI1_GROUP */
|
||||||
#if (MR_CFG_SPI2_GROUP == 1)
|
#if (MR_CFG_SPI2_GROUP == 1)
|
||||||
#define DRV_SPI2_CONFIG \
|
#define DRV_SPI2_CONFIG \
|
||||||
{SPI2, RCC_APB1Periph_SPI2, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_13, GPIOB, GPIO_Pin_14, GPIOB, GPIO_Pin_15, SPI2_IRQn, 0}
|
{SPI2, RCC_APB1Periph_SPI2, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_12, GPIOB, GPIO_Pin_13, GPIOB, GPIO_Pin_14, GPIOB, GPIO_Pin_15, SPI2_IRQn, 0}
|
||||||
#endif /* MR_CFG_SPI2_GROUP */
|
#endif /* MR_CFG_SPI2_GROUP */
|
||||||
|
|
||||||
#define DRV_TIMER1_CONFIG \
|
#define DRV_TIMER1_CONFIG \
|
||||||
|
|||||||
@@ -282,21 +282,21 @@ extern "C" {
|
|||||||
|
|
||||||
#if (MR_CFG_SPI1_GROUP == 1)
|
#if (MR_CFG_SPI1_GROUP == 1)
|
||||||
#define DRV_SPI1_CONFIG \
|
#define DRV_SPI1_CONFIG \
|
||||||
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_5, GPIOA, GPIO_Pin_6, GPIOA, GPIO_Pin_7, SPI1_IRQn, 0}
|
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_4, GPIOA, GPIO_Pin_5, GPIOA, GPIO_Pin_6, GPIOA, GPIO_Pin_7, SPI1_IRQn, 0}
|
||||||
#elif (MR_CFG_SPI1_GROUP == 2)
|
#elif (MR_CFG_SPI1_GROUP == 2)
|
||||||
#define DRV_SPI1_CONFIG \
|
#define DRV_SPI1_CONFIG \
|
||||||
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_3, GPIOB, GPIO_Pin_4, GPIOB, GPIO_Pin_5, SPI1_IRQn, GPIO_Remap_SPI1}
|
{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, GPIOA, GPIO_Pin_15, GPIOB, GPIO_Pin_3, GPIOB, GPIO_Pin_4, GPIOB, GPIO_Pin_5, SPI1_IRQn, GPIO_Remap_SPI1}
|
||||||
#endif /* MR_CFG_SPI1_GROUP */
|
#endif /* MR_CFG_SPI1_GROUP */
|
||||||
#if (MR_CFG_SPI2_GROUP == 1)
|
#if (MR_CFG_SPI2_GROUP == 1)
|
||||||
#define DRV_SPI2_CONFIG \
|
#define DRV_SPI2_CONFIG \
|
||||||
{SPI2, RCC_APB1Periph_SPI2, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_13, GPIOB, GPIO_Pin_14, GPIOB, GPIO_Pin_15, SPI2_IRQn, 0}
|
{SPI2, RCC_APB1Periph_SPI2, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_12, GPIOB, GPIO_Pin_13, GPIOB, GPIO_Pin_14, GPIOB, GPIO_Pin_15, SPI2_IRQn, 0}
|
||||||
#endif /* MR_CFG_SPI2_GROUP */
|
#endif /* MR_CFG_SPI2_GROUP */
|
||||||
#if (MR_CFG_SPI3_GROUP == 1)
|
#if (MR_CFG_SPI3_GROUP == 1)
|
||||||
#define DRV_SPI3_CONFIG \
|
#define DRV_SPI3_CONFIG \
|
||||||
{SPI3, RCC_APB1Periph_SPI3, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_3, GPIOB, GPIO_Pin_4, GPIOB, GPIO_Pin_5, SPI3_IRQn, 0}
|
{SPI3, RCC_APB1Periph_SPI3, RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, GPIOA, GPIO_Pin_15, GPIOB, GPIO_Pin_3, GPIOB, GPIO_Pin_4, GPIOB, GPIO_Pin_5, SPI3_IRQn, 0}
|
||||||
#elif (MR_CFG_SPI3_GROUP == 2)
|
#elif (MR_CFG_SPI3_GROUP == 2)
|
||||||
#define DRV_SPI3_CONFIG \
|
#define DRV_SPI3_CONFIG \
|
||||||
{SPI3, RCC_APB1Periph_SPI3, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_10, GPIOC, GPIO_Pin_11, GPIOC, GPIO_Pin_12, SPI3_IRQn, GPIO_Remap_SPI3}
|
{SPI3, RCC_APB1Periph_SPI3, RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC, GPIOA, GPIO_Pin_4, GPIOC, GPIO_Pin_10, GPIOC, GPIO_Pin_11, GPIOC, GPIO_Pin_12, SPI3_IRQn, GPIO_Remap_SPI3}
|
||||||
#endif /* MR_CFG_SPI3_GROUP */
|
#endif /* MR_CFG_SPI3_GROUP */
|
||||||
|
|
||||||
#define DRV_TIMER1_CONFIG \
|
#define DRV_TIMER1_CONFIG \
|
||||||
|
|||||||
@@ -10,6 +10,10 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_ADC
|
#ifdef MR_USING_ADC
|
||||||
|
|
||||||
|
#if !defined(MR_USING_ADC1) && !defined(MR_USING_ADC2)
|
||||||
|
#warning "Please enable at least one ADC driver"
|
||||||
|
#endif /* !defined(MR_USING_ADC1) && !defined(MR_USING_ADC2) */
|
||||||
|
|
||||||
enum drv_adc_index
|
enum drv_adc_index
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_ADC1
|
#ifdef MR_USING_ADC1
|
||||||
@@ -21,7 +25,7 @@ enum drv_adc_index
|
|||||||
DRV_INDEX_ADC_MAX
|
DRV_INDEX_ADC_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *adc_name[] =
|
static const char *adc_path[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_ADC1
|
#ifdef MR_USING_ADC1
|
||||||
"adc1",
|
"adc1",
|
||||||
@@ -153,27 +157,24 @@ static struct mr_drv adc_drv[] =
|
|||||||
{
|
{
|
||||||
#ifdef MR_USING_ADC1
|
#ifdef MR_USING_ADC1
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_ADC,
|
|
||||||
&adc_drv_ops,
|
&adc_drv_ops,
|
||||||
&adc_drv_data[DRV_INDEX_ADC1],
|
&adc_drv_data[DRV_INDEX_ADC1],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_ADC1 */
|
#endif /* MR_USING_ADC1 */
|
||||||
#ifdef MR_USING_ADC2
|
#ifdef MR_USING_ADC2
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_ADC,
|
|
||||||
&adc_drv_ops,
|
&adc_drv_ops,
|
||||||
&adc_drv_data[DRV_INDEX_ADC2],
|
&adc_drv_data[DRV_INDEX_ADC2],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_ADC2 */
|
#endif /* MR_USING_ADC2 */
|
||||||
};
|
};
|
||||||
|
|
||||||
static int drv_adc_init(void)
|
static void drv_adc_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(adc_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(adc_dev); i++)
|
||||||
{
|
{
|
||||||
mr_adc_register(&adc_dev[i], adc_name[i], &adc_drv[i]);
|
mr_adc_register(&adc_dev[i], adc_path[i], &adc_drv[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_adc_init);
|
MR_INIT_DRV_EXPORT(drv_adc_init);
|
||||||
|
|
||||||
|
|||||||
@@ -10,6 +10,10 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_DAC
|
#ifdef MR_USING_DAC
|
||||||
|
|
||||||
|
#if !defined(MR_USING_DAC1)
|
||||||
|
#warning "Please enable at least one DAC driver"
|
||||||
|
#endif /* !defined(MR_USING_DAC1) */
|
||||||
|
|
||||||
static struct drv_dac_data dac_drv_data[] =
|
static struct drv_dac_data dac_drv_data[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_DAC1
|
#ifdef MR_USING_DAC1
|
||||||
@@ -23,11 +27,7 @@ static struct mr_dac dac_dev;
|
|||||||
|
|
||||||
static struct drv_dac_channel_data *drv_dac_get_channel_data(int channel)
|
static struct drv_dac_channel_data *drv_dac_get_channel_data(int channel)
|
||||||
{
|
{
|
||||||
if (channel >= MR_ARRAY_NUM(dac_channel_drv_data))
|
if ((channel >= MR_ARRAY_NUM(dac_channel_drv_data)) || (dac_channel_drv_data[channel].port == NULL))
|
||||||
{
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
if (dac_channel_drv_data[channel].channel == 0)
|
|
||||||
{
|
{
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
@@ -144,14 +144,13 @@ static struct mr_dac_ops dac_drv_ops =
|
|||||||
|
|
||||||
static struct mr_drv dac_drv =
|
static struct mr_drv dac_drv =
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_DAC,
|
|
||||||
&dac_drv_ops,
|
&dac_drv_ops,
|
||||||
&dac_drv_data,
|
&dac_drv_data,
|
||||||
};
|
};
|
||||||
|
|
||||||
static int drv_dac_init(void)
|
static void drv_dac_init(void)
|
||||||
{
|
{
|
||||||
return mr_dac_register(&dac_dev, "dac1", &dac_drv);
|
mr_dac_register(&dac_dev, "dac1", &dac_drv);
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_dac_init);
|
MR_INIT_DRV_EXPORT(drv_dac_init);
|
||||||
|
|
||||||
|
|||||||
@@ -10,6 +10,10 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_I2C
|
#ifdef MR_USING_I2C
|
||||||
|
|
||||||
|
#if !defined(MR_USING_I2C1) && !defined(MR_USING_I2C2)
|
||||||
|
#warning "Please enable at least one I2C driver"
|
||||||
|
#endif /* !defined(MR_USING_I2C1) && !defined(MR_USING_I2C2) */
|
||||||
|
|
||||||
enum drv_i2c_index
|
enum drv_i2c_index
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_I2C1
|
#ifdef MR_USING_I2C1
|
||||||
@@ -21,7 +25,7 @@ enum drv_i2c_index
|
|||||||
DRV_INDEX_I2C_MAX
|
DRV_INDEX_I2C_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *i2c_bus_name[] =
|
static const char *i2c_bus_path[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_I2C1
|
#ifdef MR_USING_I2C1
|
||||||
"i2c1",
|
"i2c1",
|
||||||
@@ -260,27 +264,24 @@ static struct mr_drv i2c_bus_drv[] =
|
|||||||
{
|
{
|
||||||
#ifdef MR_USING_I2C1
|
#ifdef MR_USING_I2C1
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_I2C,
|
|
||||||
&i2c_bus_drv_ops,
|
&i2c_bus_drv_ops,
|
||||||
&i2c_bus_drv_data[DRV_INDEX_I2C1]
|
&i2c_bus_drv_data[DRV_INDEX_I2C1]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_I2C1 */
|
#endif /* MR_USING_I2C1 */
|
||||||
#ifdef MR_USING_I2C2
|
#ifdef MR_USING_I2C2
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_I2C,
|
|
||||||
&i2c_bus_drv_ops,
|
&i2c_bus_drv_ops,
|
||||||
&i2c_bus_drv_data[DRV_INDEX_I2C2]
|
&i2c_bus_drv_data[DRV_INDEX_I2C2]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_I2C2 */
|
#endif /* MR_USING_I2C2 */
|
||||||
};
|
};
|
||||||
|
|
||||||
static int drv_i2c_bus_init(void)
|
static void drv_i2c_bus_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(i2c_bus_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(i2c_bus_dev); i++)
|
||||||
{
|
{
|
||||||
mr_i2c_bus_register(&i2c_bus_dev[i], i2c_bus_name[i], &i2c_bus_drv[i]);
|
mr_i2c_bus_register(&i2c_bus_dev[i], i2c_bus_path[i], &i2c_bus_drv[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_i2c_bus_init);
|
MR_INIT_DRV_EXPORT(drv_i2c_bus_init);
|
||||||
|
|
||||||
|
|||||||
@@ -41,20 +41,24 @@ static struct mr_pin pin_dev;
|
|||||||
static struct drv_pin_port_data *drv_pin_get_port_data(int pin)
|
static struct drv_pin_port_data *drv_pin_get_port_data(int pin)
|
||||||
{
|
{
|
||||||
pin >>= 4;
|
pin >>= 4;
|
||||||
|
#ifdef MR_USING_PIN_CHECK
|
||||||
if ((pin >= MR_ARRAY_NUM(pin_port_drv_data)) || (pin_port_drv_data[pin].port == MR_NULL))
|
if ((pin >= MR_ARRAY_NUM(pin_port_drv_data)) || (pin_port_drv_data[pin].port == MR_NULL))
|
||||||
{
|
{
|
||||||
return MR_NULL;
|
return MR_NULL;
|
||||||
}
|
}
|
||||||
|
#endif /* MR_USING_PIN_CHECK */
|
||||||
return &pin_port_drv_data[pin];
|
return &pin_port_drv_data[pin];
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct drv_pin_data *drv_pin_get_data(int pin)
|
static struct drv_pin_data *drv_pin_get_data(int pin)
|
||||||
{
|
{
|
||||||
pin &= 0x0f;
|
pin &= 0x0f;
|
||||||
|
#ifdef MR_USING_PIN_CHECK
|
||||||
if (pin >= MR_ARRAY_NUM(pin_drv_data))
|
if (pin >= MR_ARRAY_NUM(pin_drv_data))
|
||||||
{
|
{
|
||||||
return MR_NULL;
|
return MR_NULL;
|
||||||
}
|
}
|
||||||
|
#endif /* MR_USING_PIN_CHECK */
|
||||||
return &pin_drv_data[pin];
|
return &pin_drv_data[pin];
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -67,11 +71,13 @@ static int drv_pin_configure(struct mr_pin *pin, int number, int mode)
|
|||||||
EXTI_InitTypeDef EXTI_InitStructure = {0};
|
EXTI_InitTypeDef EXTI_InitStructure = {0};
|
||||||
NVIC_InitTypeDef NVIC_InitStructure = {0};
|
NVIC_InitTypeDef NVIC_InitStructure = {0};
|
||||||
|
|
||||||
|
#ifdef MR_USING_PIN_CHECK
|
||||||
/* Check pin is valid */
|
/* Check pin is valid */
|
||||||
if (pin_port_data == MR_NULL || pin_data == MR_NULL)
|
if (pin_port_data == MR_NULL || pin_data == MR_NULL)
|
||||||
{
|
{
|
||||||
return MR_EINVAL;
|
return MR_EINVAL;
|
||||||
}
|
}
|
||||||
|
#endif /* MR_USING_PIN_CHECK */
|
||||||
|
|
||||||
/* Configure clock */
|
/* Configure clock */
|
||||||
#ifdef GPIOA
|
#ifdef GPIOA
|
||||||
@@ -250,11 +256,13 @@ static uint8_t drv_pin_read(struct mr_pin *pin, int number)
|
|||||||
struct drv_pin_port_data *pin_port_data = drv_pin_get_port_data(number);
|
struct drv_pin_port_data *pin_port_data = drv_pin_get_port_data(number);
|
||||||
struct drv_pin_data *pin_data = drv_pin_get_data(number);
|
struct drv_pin_data *pin_data = drv_pin_get_data(number);
|
||||||
|
|
||||||
|
#ifdef MR_USING_PIN_CHECK
|
||||||
/* Check pin is valid */
|
/* Check pin is valid */
|
||||||
if (pin_port_data == NULL || pin_data == NULL)
|
if (pin_port_data == NULL || pin_data == NULL)
|
||||||
{
|
{
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
#endif /* MR_USING_PIN_CHECK */
|
||||||
return (int)GPIO_ReadInputDataBit(pin_port_data->port, pin_data->pin);
|
return (int)GPIO_ReadInputDataBit(pin_port_data->port, pin_data->pin);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -263,11 +271,13 @@ static void drv_pin_write(struct mr_pin *pin, int number, uint8_t value)
|
|||||||
struct drv_pin_port_data *pin_port_data = drv_pin_get_port_data(number);
|
struct drv_pin_port_data *pin_port_data = drv_pin_get_port_data(number);
|
||||||
struct drv_pin_data *pin_data = drv_pin_get_data(number);
|
struct drv_pin_data *pin_data = drv_pin_get_data(number);
|
||||||
|
|
||||||
|
#ifdef MR_USING_PIN_CHECK
|
||||||
/* Check pin is valid */
|
/* Check pin is valid */
|
||||||
if (pin_port_data == NULL || pin_data == NULL)
|
if (pin_port_data == NULL || pin_data == NULL)
|
||||||
{
|
{
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
#endif /* MR_USING_PIN_CHECK */
|
||||||
GPIO_WriteBit(pin_port_data->port, pin_data->pin, value);
|
GPIO_WriteBit(pin_port_data->port, pin_data->pin, value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -442,14 +452,13 @@ static struct mr_pin_ops pin_drv_ops =
|
|||||||
|
|
||||||
static struct mr_drv pin_drv =
|
static struct mr_drv pin_drv =
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Pin,
|
|
||||||
&pin_drv_ops,
|
&pin_drv_ops,
|
||||||
MR_NULL
|
MR_NULL
|
||||||
};
|
};
|
||||||
|
|
||||||
static int drv_pin_init(void)
|
static void drv_pin_init(void)
|
||||||
{
|
{
|
||||||
return mr_pin_register(&pin_dev, "pin", &pin_drv);
|
mr_pin_register(&pin_dev, "pin", &pin_drv);
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_pin_init);
|
MR_INIT_DRV_EXPORT(drv_pin_init);
|
||||||
|
|
||||||
|
|||||||
@@ -10,6 +10,12 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_PWM
|
#ifdef MR_USING_PWM
|
||||||
|
|
||||||
|
#if !defined(MR_USING_PWM1) && !defined(MR_USING_PWM2) && !defined(MR_USING_PWM3) && !defined(MR_USING_PWM4) && \
|
||||||
|
!defined(MR_USING_PWM5) && !defined(MR_USING_PWM8) && !defined(MR_USING_PWM9) && !defined(MR_USING_PWM10)
|
||||||
|
#warning "Please enable at least one PWM driver"
|
||||||
|
#endif /* !defined(MR_USING_PWM1) && !defined(MR_USING_PWM2) && !defined(MR_USING_PWM3) && !defined(MR_USING_PWM4) &&
|
||||||
|
* !defined(MR_USING_PWM5) && !defined(MR_USING_PWM8) && !defined(MR_USING_PWM9) && !defined(MR_USING_PWM10) */
|
||||||
|
|
||||||
enum drv_pwm_index
|
enum drv_pwm_index
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_PWM1
|
#ifdef MR_USING_PWM1
|
||||||
@@ -39,7 +45,7 @@ enum drv_pwm_index
|
|||||||
DRV_INDEX_PWM_MAX
|
DRV_INDEX_PWM_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *pwm_name[] =
|
static const char *pwm_path[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_PWM1
|
#ifdef MR_USING_PWM1
|
||||||
"pwm1",
|
"pwm1",
|
||||||
@@ -314,69 +320,60 @@ static struct mr_drv pwm_drv[] =
|
|||||||
{
|
{
|
||||||
#ifdef MR_USING_PWM1
|
#ifdef MR_USING_PWM1
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM1]
|
&pwm_drv_data[DRV_INDEX_PWM1]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM1 */
|
#endif /* MR_USING_PWM1 */
|
||||||
#ifdef MR_USING_PWM2
|
#ifdef MR_USING_PWM2
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM2]
|
&pwm_drv_data[DRV_INDEX_PWM2]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM2 */
|
#endif /* MR_USING_PWM2 */
|
||||||
#ifdef MR_USING_PWM3
|
#ifdef MR_USING_PWM3
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM3]
|
&pwm_drv_data[DRV_INDEX_PWM3]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM3 */
|
#endif /* MR_USING_PWM3 */
|
||||||
#ifdef MR_USING_PWM4
|
#ifdef MR_USING_PWM4
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM4]
|
&pwm_drv_data[DRV_INDEX_PWM4]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM4 */
|
#endif /* MR_USING_PWM4 */
|
||||||
#ifdef MR_USING_PWM5
|
#ifdef MR_USING_PWM5
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM5]
|
&pwm_drv_data[DRV_INDEX_PWM5]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM5 */
|
#endif /* MR_USING_PWM5 */
|
||||||
#ifdef MR_USING_PWM8
|
#ifdef MR_USING_PWM8
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM8]
|
&pwm_drv_data[DRV_INDEX_PWM8]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM8 */
|
#endif /* MR_USING_PWM8 */
|
||||||
#ifdef MR_USING_PWM9
|
#ifdef MR_USING_PWM9
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM9]
|
&pwm_drv_data[DRV_INDEX_PWM9]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM9 */
|
#endif /* MR_USING_PWM9 */
|
||||||
#ifdef MR_USING_PWM10
|
#ifdef MR_USING_PWM10
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_PWM,
|
|
||||||
&pwm_drv_ops,
|
&pwm_drv_ops,
|
||||||
&pwm_drv_data[DRV_INDEX_PWM10]
|
&pwm_drv_data[DRV_INDEX_PWM10]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_PWM10 */
|
#endif /* MR_USING_PWM10 */
|
||||||
};
|
};
|
||||||
|
|
||||||
static int drv_pwm_init(void)
|
static void drv_pwm_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(pwm_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(pwm_dev); i++)
|
||||||
{
|
{
|
||||||
mr_pwm_register(&pwm_dev[i], pwm_name[i], &pwm_drv[i], &pwm_info[i]);
|
mr_pwm_register(&pwm_dev[i], pwm_path[i], &pwm_drv[i], &pwm_info[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_pwm_init);
|
MR_INIT_DRV_EXPORT(drv_pwm_init);
|
||||||
|
|
||||||
|
|||||||
@@ -10,6 +10,12 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_SERIAL
|
#ifdef MR_USING_SERIAL
|
||||||
|
|
||||||
|
#if !defined(MR_USING_UART1) && !defined(MR_USING_UART2) && !defined(MR_USING_UART3) && !defined(MR_USING_UART4) && \
|
||||||
|
!defined(MR_USING_UART5) && !defined(MR_USING_UART6) && !defined(MR_USING_UART7) && !defined(MR_USING_UART8)
|
||||||
|
#warning "Please enable at least one Serial driver"
|
||||||
|
#endif /* !defined(MR_USING_UART1) && !defined(MR_USING_UART2) && !defined(MR_USING_UART3) && !defined(MR_USING_UART4) && \
|
||||||
|
* !defined(MR_USING_UART5) && !defined(MR_USING_UART6) && !defined(MR_USING_UART7) && !defined(MR_USING_UART8) */
|
||||||
|
|
||||||
enum drv_serial_index
|
enum drv_serial_index
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_UART1
|
#ifdef MR_USING_UART1
|
||||||
@@ -39,7 +45,7 @@ enum drv_serial_index
|
|||||||
DRV_INDEX_UART_MAX
|
DRV_INDEX_UART_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *serial_name[] =
|
static const char *serial_path[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_UART1
|
#ifdef MR_USING_UART1
|
||||||
"serial1",
|
"serial1",
|
||||||
@@ -396,69 +402,60 @@ static struct mr_drv serial_drv[] =
|
|||||||
{
|
{
|
||||||
#ifdef MR_USING_UART1
|
#ifdef MR_USING_UART1
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART1]
|
&serial_drv_data[DRV_INDEX_UART1]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART1 */
|
#endif /* MR_USING_UART1 */
|
||||||
#ifdef MR_USING_UART2
|
#ifdef MR_USING_UART2
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART2]
|
&serial_drv_data[DRV_INDEX_UART2]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART2 */
|
#endif /* MR_USING_UART2 */
|
||||||
#ifdef MR_USING_UART3
|
#ifdef MR_USING_UART3
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART3]
|
&serial_drv_data[DRV_INDEX_UART3]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART3 */
|
#endif /* MR_USING_UART3 */
|
||||||
#ifdef MR_USING_UART4
|
#ifdef MR_USING_UART4
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART4]
|
&serial_drv_data[DRV_INDEX_UART4]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART4 */
|
#endif /* MR_USING_UART4 */
|
||||||
#ifdef MR_USING_UART5
|
#ifdef MR_USING_UART5
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART5]
|
&serial_drv_data[DRV_INDEX_UART5]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART5 */
|
#endif /* MR_USING_UART5 */
|
||||||
#ifdef MR_USING_UART6
|
#ifdef MR_USING_UART6
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART6]
|
&serial_drv_data[DRV_INDEX_UART6]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART6 */
|
#endif /* MR_USING_UART6 */
|
||||||
#ifdef MR_USING_UART7
|
#ifdef MR_USING_UART7
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART7]
|
&serial_drv_data[DRV_INDEX_UART7]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART7 */
|
#endif /* MR_USING_UART7 */
|
||||||
#ifdef MR_USING_UART8
|
#ifdef MR_USING_UART8
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Serial,
|
|
||||||
&serial_drv_ops,
|
&serial_drv_ops,
|
||||||
&serial_drv_data[DRV_INDEX_UART8]
|
&serial_drv_data[DRV_INDEX_UART8]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_UART8 */
|
#endif /* MR_USING_UART8 */
|
||||||
};
|
};
|
||||||
|
|
||||||
static int drv_serial_init(void)
|
static void drv_serial_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(serial_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(serial_dev); i++)
|
||||||
{
|
{
|
||||||
mr_serial_register(&serial_dev[i], serial_name[i], &serial_drv[i]);
|
mr_serial_register(&serial_dev[i], serial_path[i], &serial_drv[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_serial_init);
|
MR_INIT_DRV_EXPORT(drv_serial_init);
|
||||||
|
|
||||||
|
|||||||
@@ -10,6 +10,10 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_SPI
|
#ifdef MR_USING_SPI
|
||||||
|
|
||||||
|
#if !defined(MR_USING_SPI1) && !defined(MR_USING_SPI2) && !defined(MR_USING_SPI3)
|
||||||
|
#warning "Please enable at least one SPI driver"
|
||||||
|
#endif /* !defined(MR_USING_SPI1) && !defined(MR_USING_SPI2) && !defined(MR_USING_SPI3) */
|
||||||
|
|
||||||
enum drv_spi_bus_index
|
enum drv_spi_bus_index
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_SPI1
|
#ifdef MR_USING_SPI1
|
||||||
@@ -24,7 +28,7 @@ enum drv_spi_bus_index
|
|||||||
DRV_INDEX_SPI_MAX
|
DRV_INDEX_SPI_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *spi_bus_name[] =
|
static const char *spi_bus_path[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_SPI1
|
#ifdef MR_USING_SPI1
|
||||||
"spi1",
|
"spi1",
|
||||||
@@ -75,6 +79,15 @@ static int drv_spi_bus_configure(struct mr_spi_bus *spi_bus, struct mr_spi_confi
|
|||||||
pclk = RCC_ClockStructure.PCLK1_Frequency;
|
pclk = RCC_ClockStructure.PCLK1_Frequency;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Configure remap */
|
||||||
|
if (spi_bus_data->remap != 0)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||||
|
GPIO_PinRemapConfig(spi_bus_data->remap, state);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (state == ENABLE)
|
||||||
|
{
|
||||||
psc = pclk / config->baud_rate;
|
psc = pclk / config->baud_rate;
|
||||||
if (psc >= 256)
|
if (psc >= 256)
|
||||||
{
|
{
|
||||||
@@ -102,20 +115,12 @@ static int drv_spi_bus_configure(struct mr_spi_bus *spi_bus, struct mr_spi_confi
|
|||||||
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Configure remap */
|
|
||||||
if (spi_bus_data->remap != 0)
|
|
||||||
{
|
|
||||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
|
|
||||||
GPIO_PinRemapConfig(spi_bus_data->remap, state);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (state == ENABLE)
|
|
||||||
{
|
|
||||||
switch (config->host_slave)
|
switch (config->host_slave)
|
||||||
{
|
{
|
||||||
case MR_SPI_HOST:
|
case MR_SPI_HOST:
|
||||||
{
|
{
|
||||||
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
|
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
|
||||||
|
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
|
||||||
|
|
||||||
GPIO_InitStructure.GPIO_Pin = spi_bus_data->sck_pin;
|
GPIO_InitStructure.GPIO_Pin = spi_bus_data->sck_pin;
|
||||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||||
@@ -135,6 +140,11 @@ static int drv_spi_bus_configure(struct mr_spi_bus *spi_bus, struct mr_spi_confi
|
|||||||
case MR_SPI_SLAVE:
|
case MR_SPI_SLAVE:
|
||||||
{
|
{
|
||||||
SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
|
SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
|
||||||
|
SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = spi_bus_data->nss_pin;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||||
|
GPIO_Init(spi_bus_data->nss_port, &GPIO_InitStructure);
|
||||||
|
|
||||||
GPIO_InitStructure.GPIO_Pin = spi_bus_data->sck_pin;
|
GPIO_InitStructure.GPIO_Pin = spi_bus_data->sck_pin;
|
||||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||||
@@ -225,6 +235,13 @@ static int drv_spi_bus_configure(struct mr_spi_bus *spi_bus, struct mr_spi_confi
|
|||||||
}
|
}
|
||||||
} else
|
} else
|
||||||
{
|
{
|
||||||
|
if (config->host_slave == MR_SPI_SLAVE)
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = spi_bus_data->nss_pin;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||||
|
GPIO_Init(spi_bus_data->nss_port, &GPIO_InitStructure);
|
||||||
|
}
|
||||||
|
|
||||||
GPIO_InitStructure.GPIO_Pin = spi_bus_data->sck_pin;
|
GPIO_InitStructure.GPIO_Pin = spi_bus_data->sck_pin;
|
||||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||||
GPIO_Init(spi_bus_data->sck_port, &GPIO_InitStructure);
|
GPIO_Init(spi_bus_data->sck_port, &GPIO_InitStructure);
|
||||||
@@ -239,7 +256,6 @@ static int drv_spi_bus_configure(struct mr_spi_bus *spi_bus, struct mr_spi_confi
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Configure SPI */
|
/* Configure SPI */
|
||||||
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
|
|
||||||
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||||
SPI_InitStructure.SPI_CRCPolynomial = 7;
|
SPI_InitStructure.SPI_CRCPolynomial = 7;
|
||||||
SPI_Init(spi_bus_data->instance, &SPI_InitStructure);
|
SPI_Init(spi_bus_data->instance, &SPI_InitStructure);
|
||||||
@@ -342,34 +358,30 @@ static struct mr_drv spi_bus_drv[] =
|
|||||||
{
|
{
|
||||||
#ifdef MR_USING_SPI1
|
#ifdef MR_USING_SPI1
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_SPI,
|
|
||||||
&spi_bus_drv_ops,
|
&spi_bus_drv_ops,
|
||||||
&spi_bus_drv_data[DRV_INDEX_SPI1],
|
&spi_bus_drv_data[DRV_INDEX_SPI1],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_SPI1 */
|
#endif /* MR_USING_SPI1 */
|
||||||
#ifdef MR_USING_SPI2
|
#ifdef MR_USING_SPI2
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_SPI,
|
|
||||||
&spi_bus_drv_ops,
|
&spi_bus_drv_ops,
|
||||||
&spi_bus_drv_data[DRV_INDEX_SPI2],
|
&spi_bus_drv_data[DRV_INDEX_SPI2],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_SPI2 */
|
#endif /* MR_USING_SPI2 */
|
||||||
#ifdef MR_USING_SPI3
|
#ifdef MR_USING_SPI3
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_SPI,
|
|
||||||
&spi_bus_drv_ops,
|
&spi_bus_drv_ops,
|
||||||
&spi_bus_drv_data[DRV_INDEX_SPI3],
|
&spi_bus_drv_data[DRV_INDEX_SPI3],
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_SPI3 */
|
#endif /* MR_USING_SPI3 */
|
||||||
};
|
};
|
||||||
|
|
||||||
static int drv_spi_bus_init(void)
|
static void drv_spi_bus_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(spi_bus_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(spi_bus_dev); i++)
|
||||||
{
|
{
|
||||||
mr_spi_bus_register(&spi_bus_dev[i], spi_bus_name[i], &spi_bus_drv[i]);
|
mr_spi_bus_register(&spi_bus_dev[i], spi_bus_path[i], &spi_bus_drv[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_spi_bus_init);
|
MR_INIT_DRV_EXPORT(drv_spi_bus_init);
|
||||||
|
|
||||||
|
|||||||
@@ -23,6 +23,8 @@ struct drv_spi_bus_data
|
|||||||
SPI_TypeDef *instance;
|
SPI_TypeDef *instance;
|
||||||
uint32_t clock;
|
uint32_t clock;
|
||||||
uint32_t gpio_clock;
|
uint32_t gpio_clock;
|
||||||
|
GPIO_TypeDef *nss_port;
|
||||||
|
uint32_t nss_pin;
|
||||||
GPIO_TypeDef *sck_port;
|
GPIO_TypeDef *sck_port;
|
||||||
uint32_t sck_pin;
|
uint32_t sck_pin;
|
||||||
GPIO_TypeDef *miso_port;
|
GPIO_TypeDef *miso_port;
|
||||||
|
|||||||
@@ -10,6 +10,12 @@
|
|||||||
|
|
||||||
#ifdef MR_USING_TIMER
|
#ifdef MR_USING_TIMER
|
||||||
|
|
||||||
|
#if !defined(MR_USING_TIMER1) && !defined(MR_USING_TIMER2) && !defined(MR_USING_TIMER3) && !defined(MR_USING_TIMER4) && \
|
||||||
|
!defined(MR_USING_TIMER5) && !defined(MR_USING_TIMER8) && !defined(MR_USING_TIMER9) && !defined(MR_USING_TIMER10)
|
||||||
|
#warning "Please enable at least one Timer driver"
|
||||||
|
#endif /* !defined(MR_USING_TIMER1) && !defined(MR_USING_TIMER2) && !defined(MR_USING_TIMER3) && !defined(MR_USING_TIMER4) &&
|
||||||
|
* !defined(MR_USING_TIMER5) && !defined(MR_USING_TIMER8) && !defined(MR_USING_TIMER9) && !defined(MR_USING_TIMER10) */
|
||||||
|
|
||||||
enum drv_timer_index
|
enum drv_timer_index
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_TIMER1
|
#ifdef MR_USING_TIMER1
|
||||||
@@ -45,7 +51,7 @@ enum drv_timer_index
|
|||||||
DRV_INDEX_TIMER_MAX
|
DRV_INDEX_TIMER_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *timer_name[] =
|
static const char *timer_path[] =
|
||||||
{
|
{
|
||||||
#ifdef MR_USING_TIMER1
|
#ifdef MR_USING_TIMER1
|
||||||
"timer1",
|
"timer1",
|
||||||
@@ -326,83 +332,72 @@ static struct mr_drv timer_drv[] =
|
|||||||
{
|
{
|
||||||
#ifdef MR_USING_TIMER1
|
#ifdef MR_USING_TIMER1
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER1]
|
&timer_drv_data[DRV_INDEX_TIMER1]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER1 */
|
#endif /* MR_USING_TIMER1 */
|
||||||
#ifdef MR_USING_TIMER2
|
#ifdef MR_USING_TIMER2
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER2]
|
&timer_drv_data[DRV_INDEX_TIMER2]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER2 */
|
#endif /* MR_USING_TIMER2 */
|
||||||
#ifdef MR_USING_TIMER3
|
#ifdef MR_USING_TIMER3
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER3]
|
&timer_drv_data[DRV_INDEX_TIMER3]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER3 */
|
#endif /* MR_USING_TIMER3 */
|
||||||
#ifdef MR_USING_TIMER4
|
#ifdef MR_USING_TIMER4
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER4]
|
&timer_drv_data[DRV_INDEX_TIMER4]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER4 */
|
#endif /* MR_USING_TIMER4 */
|
||||||
#ifdef MR_USING_TIMER5
|
#ifdef MR_USING_TIMER5
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER5]
|
&timer_drv_data[DRV_INDEX_TIMER5]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER5 */
|
#endif /* MR_USING_TIMER5 */
|
||||||
#ifdef MR_USING_TIMER6
|
#ifdef MR_USING_TIMER6
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER6]
|
&timer_drv_data[DRV_INDEX_TIMER6]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER6 */
|
#endif /* MR_USING_TIMER6 */
|
||||||
#ifdef MR_USING_TIMER7
|
#ifdef MR_USING_TIMER7
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER7]
|
&timer_drv_data[DRV_INDEX_TIMER7]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER7 */
|
#endif /* MR_USING_TIMER7 */
|
||||||
#ifdef MR_USING_TIMER8
|
#ifdef MR_USING_TIMER8
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER8]
|
&timer_drv_data[DRV_INDEX_TIMER8]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER8 */
|
#endif /* MR_USING_TIMER8 */
|
||||||
#ifdef MR_USING_TIMER9
|
#ifdef MR_USING_TIMER9
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER9]
|
&timer_drv_data[DRV_INDEX_TIMER9]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER9 */
|
#endif /* MR_USING_TIMER9 */
|
||||||
#ifdef MR_USING_TIMER10
|
#ifdef MR_USING_TIMER10
|
||||||
{
|
{
|
||||||
Mr_Drv_Type_Timer,
|
|
||||||
&timer_drv_ops,
|
&timer_drv_ops,
|
||||||
&timer_drv_data[DRV_INDEX_TIMER10]
|
&timer_drv_data[DRV_INDEX_TIMER10]
|
||||||
},
|
},
|
||||||
#endif /* MR_USING_TIMER10 */
|
#endif /* MR_USING_TIMER10 */
|
||||||
};
|
};
|
||||||
|
|
||||||
static int drv_timer_init(void)
|
static void drv_timer_init(void)
|
||||||
{
|
{
|
||||||
for (size_t i = 0; i < MR_ARRAY_NUM(timer_dev); i++)
|
for (size_t i = 0; i < MR_ARRAY_NUM(timer_dev); i++)
|
||||||
{
|
{
|
||||||
mr_timer_register(&timer_dev[i], timer_name[i], &timer_drv[i], &timer_info[i]);
|
mr_timer_register(&timer_dev[i], timer_path[i], &timer_drv[i], &timer_info[i]);
|
||||||
}
|
}
|
||||||
return MR_EOK;
|
|
||||||
}
|
}
|
||||||
MR_INIT_DRV_EXPORT(drv_timer_init);
|
MR_INIT_DRV_EXPORT(drv_timer_init);
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user