1.新增STM32-SPI驱动。
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MacRsh
388
bsp/st/driver/drv_spi.c
Normal file
388
bsp/st/driver/drv_spi.c
Normal file
@@ -0,0 +1,388 @@
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/*
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* Copyright (c) 2023, mr-library Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-10-8 MacRsh first version
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*/
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#include "drv_spi.h"
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#if (MR_CFG_SPI == MR_CFG_ENABLE)
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#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0x0Fu))
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#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
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#define PIN_STPIN(pin) ((uint16_t)(1u << (mr_uint8_t)(pin & 0x0Fu)))
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enum drv_spi_index
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{
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#ifdef MR_BSP_SPI_1
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DRV_SPI_1_INDEX,
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#endif
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#ifdef MR_BSP_SPI_2
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DRV_SPI_2_INDEX,
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#endif
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#ifdef MR_BSP_SPI_3
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DRV_SPI_3_INDEX,
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#endif
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#ifdef MR_BSP_SPI_4
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DRV_SPI_4_INDEX,
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#endif
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#ifdef MR_BSP_SPI_5
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DRV_SPI_5_INDEX,
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#endif
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#ifdef MR_BSP_SPI_6
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DRV_SPI_6_INDEX,
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#endif
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};
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static struct drv_spi_bus_data drv_spi_bus_data[] =
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{
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#ifdef MR_BSP_SPI_1
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{"spi1", {0}, SPI1, SPI1_IRQn},
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#endif
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#ifdef MR_BSP_SPI_2
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{"spi2", {0}, SPI2, SPI2_IRQn},
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#endif
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#ifdef MR_BSP_SPI_3
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{"spi3", {0}, SPI3, SPI3_IRQn},
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#endif
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#ifdef MR_BSP_SPI_4
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{"spi4", {0}, SPI4, SPI4_IRQn},
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#endif
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#ifdef MR_BSP_SPI_5
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{"spi5", {0}, SPI5, SPI5_IRQn},
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#endif
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#ifdef MR_BSP_SPI_6
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{"spi6", {0}, SPI6, SPI6_IRQn},
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#endif
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};
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static struct mr_spi_bus spi_bus_device[mr_array_num(drv_spi_bus_data)];
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static mr_uint16_t stm32_spi_baud_rate_prescaler(mr_uint32_t pclk_freq, mr_uint32_t baud_rate)
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{
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mr_uint32_t psc = pclk_freq / baud_rate;
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if (psc >= 256)
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{
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return SPI_BAUDRATEPRESCALER_256;
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} else if (psc >= 128)
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{
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return SPI_BAUDRATEPRESCALER_128;
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} else if (psc >= 64)
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{
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return SPI_BAUDRATEPRESCALER_64;
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} else if (psc >= 32)
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{
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return SPI_BAUDRATEPRESCALER_32;
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} else if (psc >= 16)
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{
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return SPI_BAUDRATEPRESCALER_16;
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} else if (psc >= 8)
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{
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return SPI_BAUDRATEPRESCALER_8;
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} else if (psc >= 4)
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{
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return SPI_BAUDRATEPRESCALER_4;
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} else if (psc >= 2)
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{
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return SPI_BAUDRATEPRESCALER_2;
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}
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return SPI_BAUDRATEPRESCALER_2;
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}
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static mr_err_t drv_spi_configure(mr_spi_bus_t spi_bus, mr_spi_config_t config)
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{
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struct drv_spi_bus_data *spi_bus_data = (struct drv_spi_bus_data *)spi_bus->device.data;
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mr_uint32_t pclk_freq = 0;
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if ((uint32_t)spi_bus_data->instance > APB2PERIPH_BASE)
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{
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pclk_freq = HAL_RCC_GetPCLK2Freq();
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} else
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{
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pclk_freq = HAL_RCC_GetPCLK1Freq();
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}
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spi_bus_data->handle.Instance = spi_bus_data->instance;
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switch (config->host_slave)
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{
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case MR_SPI_HOST:
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{
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spi_bus_data->handle.Init.Mode = SPI_MODE_MASTER;
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break;
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}
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case MR_SPI_SLAVE:
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{
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spi_bus_data->handle.Init.Mode = SPI_MODE_SLAVE;
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break;
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}
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default:
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return MR_ERR_INVALID;
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}
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switch (config->mode)
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{
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case MR_SPI_MODE_0:
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{
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spi_bus_data->handle.Init.CLKPolarity = SPI_POLARITY_LOW;
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spi_bus_data->handle.Init.CLKPhase = SPI_PHASE_1EDGE;
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break;
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}
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case MR_SPI_MODE_1:
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{
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spi_bus_data->handle.Init.CLKPolarity = SPI_POLARITY_LOW;
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spi_bus_data->handle.Init.CLKPhase = SPI_PHASE_2EDGE;
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break;
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}
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case MR_SPI_MODE_2:
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{
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spi_bus_data->handle.Init.CLKPolarity = SPI_POLARITY_HIGH;
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spi_bus_data->handle.Init.CLKPhase = SPI_PHASE_1EDGE;
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break;
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}
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case MR_SPI_MODE_3:
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{
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spi_bus_data->handle.Init.CLKPolarity = SPI_POLARITY_HIGH;
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spi_bus_data->handle.Init.CLKPhase = SPI_PHASE_2EDGE;
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break;
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}
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default:
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return MR_ERR_INVALID;
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}
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switch (config->data_bits)
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{
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case MR_SPI_DATA_BITS_8:
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{
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spi_bus_data->handle.Init.DataSize = SPI_DATASIZE_8BIT;
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break;
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}
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case MR_SPI_DATA_BITS_16:
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{
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spi_bus_data->handle.Init.DataSize = SPI_DATASIZE_16BIT;
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break;
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}
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default:
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return MR_ERR_INVALID;
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}
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switch (config->bit_order)
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{
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case MR_SPI_BIT_ORDER_LSB:
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{
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spi_bus_data->handle.Init.FirstBit = SPI_FIRSTBIT_LSB;
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break;
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}
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case MR_SPI_BIT_ORDER_MSB:
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{
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spi_bus_data->handle.Init.FirstBit = SPI_FIRSTBIT_MSB;
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break;
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}
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default:
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return MR_ERR_INVALID;
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}
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switch (config->cs_active)
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{
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case MR_SPI_CS_ACTIVE_LOW:
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case MR_SPI_CS_ACTIVE_HIGH:
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{
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spi_bus_data->handle.Init.NSS = SPI_NSS_SOFT;
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break;
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}
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case MR_SPI_CS_ACTIVE_HARDWARE:
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{
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if (config->host_slave == MR_SPI_HOST)
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{
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spi_bus_data->handle.Init.NSS = SPI_NSS_HARD_OUTPUT;
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} else
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{
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spi_bus_data->handle.Init.NSS = SPI_NSS_HARD_INPUT;
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}
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break;
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}
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default:
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return MR_ERR_INVALID;
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}
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spi_bus_data->handle.Init.BaudRatePrescaler = stm32_spi_baud_rate_prescaler(pclk_freq, config->baud_rate);
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spi_bus_data->handle.Init.Direction = SPI_DIRECTION_2LINES;
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spi_bus_data->handle.Init.TIMode = SPI_TIMODE_DISABLE;
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spi_bus_data->handle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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spi_bus_data->handle.Init.CRCPolynomial = 7;
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if (HAL_SPI_Init(&spi_bus_data->handle) != HAL_OK)
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{
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return MR_ERR_GENERIC;
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}
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if (config->baud_rate != 0)
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{
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__HAL_SPI_ENABLE(&spi_bus_data->handle);
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} else
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{
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__HAL_SPI_DISABLE(&spi_bus_data->handle);
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}
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if (config->host_slave == MR_SPI_HOST)
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{
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HAL_NVIC_SetPriority(spi_bus_data->irq_type, 1, 0);
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HAL_NVIC_DisableIRQ(spi_bus_data->irq_type);
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__HAL_UART_DISABLE_IT(&spi_bus_data->handle, SPI_IT_RXNE);
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} else
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{
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HAL_NVIC_SetPriority(spi_bus_data->irq_type, 1, 0);
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HAL_NVIC_EnableIRQ(spi_bus_data->irq_type);
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__HAL_UART_ENABLE_IT(&spi_bus_data->handle, SPI_IT_RXNE);
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}
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return MR_ERR_OK;
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}
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static void drv_spi_write(mr_spi_bus_t spi_bus, mr_uint32_t data)
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{
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struct drv_spi_bus_data *spi_bus_data = (struct drv_spi_bus_data *)spi_bus->device.data;
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mr_size_t i = 0;
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while (__HAL_SPI_GET_FLAG(&spi_bus_data->handle, SPI_FLAG_TXE) == RESET)
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{
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i++;
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if (i > MR_UINT16_MAX)
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{
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return;
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}
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}
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spi_bus_data->instance->DR = data;
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}
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static mr_uint32_t drv_spi_read(mr_spi_bus_t spi_bus)
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{
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struct drv_spi_bus_data *spi_bus_data = (struct drv_spi_bus_data *)spi_bus->device.data;
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mr_size_t i = 0;
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while (__HAL_SPI_GET_FLAG(&spi_bus_data->handle, SPI_FLAG_RXNE) == RESET)
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{
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i++;
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if (i > MR_UINT16_MAX)
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{
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return 0;
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}
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}
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return (mr_uint32_t)spi_bus_data->instance->DR;
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}
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static void drv_spi_cs_write(mr_spi_bus_t spi_bus, mr_off_t cs_number, mr_level_t level)
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{
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if (cs_number > MR_BSP_PIN_NUMBER)
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{
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return;
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}
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HAL_GPIO_WritePin(PIN_STPORT(cs_number), PIN_STPIN(cs_number), (GPIO_PinState)level);
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}
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static mr_level_t drv_spi_cs_read(mr_spi_bus_t spi_bus, mr_off_t cs_number)
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{
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if (cs_number > MR_BSP_PIN_NUMBER)
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{
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return 0;
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}
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return (mr_level_t)HAL_GPIO_ReadPin(PIN_STPORT(cs_number), PIN_STPIN(cs_number));
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}
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static void drv_spi_isr(mr_spi_bus_t spi_bus)
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{
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struct drv_spi_bus_data *spi_bus_data = (struct drv_spi_bus_data *)spi_bus->device.data;
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if (__HAL_UART_GET_FLAG(&spi_bus_data->handle, SPI_FLAG_RXNE) != RESET &&
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__HAL_UART_GET_IT_SOURCE(&spi_bus_data->handle, SPI_IT_RXNE) != RESET)
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{
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mr_spi_bus_isr(spi_bus, MR_SPI_BUS_EVENT_RX_INT);
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}
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}
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#ifdef MR_BSP_SPI_1
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void SPI1_IRQHandler(void)
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{
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drv_spi_isr(&spi_bus_device[DRV_SPI_1_INDEX]);
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}
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#endif
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#ifdef MR_BSP_SPI_2
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void SPI2_IRQHandler(void)
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{
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drv_spi_isr(&spi_bus_device[DRV_SPI_2_INDEX]);
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}
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#endif
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#ifdef MR_BSP_SPI_3
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void SPI3_IRQHandler(void)
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{
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drv_spi_isr(&spi_bus_device[DRV_SPI_3_INDEX]);
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}
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#endif
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#ifdef MR_BSP_SPI_4
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void SPI4_IRQHandler(void)
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{
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drv_spi_isr(&spi_bus_device[DRV_SPI_4_INDEX]);
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}
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#endif
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#ifdef MR_BSP_SPI_5
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void SPI5_IRQHandler(void)
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{
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drv_spi_isr(&spi_bus_device[DRV_SPI_5_INDEX]);
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}
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#endif
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#ifdef MR_BSP_SPI_6
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void SPI6_IRQHandler(void)
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{
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drv_spi_isr(&spi_bus_device[DRV_SPI_6_INDEX]);
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}
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#endif
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mr_err_t drv_spi_bus_init(void)
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{
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static struct mr_spi_bus_ops drv_ops =
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{
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drv_spi_configure,
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drv_spi_write,
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drv_spi_read,
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drv_spi_cs_write,
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drv_spi_cs_read,
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};
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mr_size_t count = mr_array_num(spi_bus_device);
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mr_err_t ret = MR_ERR_OK;
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while (count--)
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{
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ret =
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mr_spi_bus_add(&spi_bus_device[count], drv_spi_bus_data[count].name, &drv_ops, &drv_spi_bus_data[count]);
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MR_ASSERT(ret == MR_ERR_OK);
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}
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return ret;
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}
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MR_INIT_DRIVER_EXPORT(drv_spi_bus_init);
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#endif
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33
bsp/st/driver/drv_spi.h
Normal file
33
bsp/st/driver/drv_spi.h
Normal file
@@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2023, mr-library Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-10-8 MacRsh first version
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*/
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#ifndef _DRV_SPI_H_
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#define _DRV_SPI_H_
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#include "device/spi.h"
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#include "mrboard.h"
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#if (MR_CFG_SPI == MR_CFG_ENABLE)
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/**
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* @struct Driver spi bus data
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*/
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struct drv_spi_bus_data
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{
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const char *name;
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SPI_HandleTypeDef handle;
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SPI_TypeDef *instance;
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IRQn_Type irq_type;
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};
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#endif
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#endif /* _DRV_SPI_H_ */
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