1.新增ST ADC驱动。
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MacRsh
@@ -1,7 +1,67 @@
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menu "Board configure"
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menu "GPIO"
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choice
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prompt "Chip type"
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default MR_USING_STM32F1
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config MR_USING_STM32F0
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bool "STM32F0"
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config MR_USING_STM32F1
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bool "STM32F1"
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config MR_USING_STM32F2
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bool "STM32F2"
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config MR_USING_STM32F3
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bool "STM32F3"
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config MR_USING_STM32F4
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bool "STM32F4"
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config MR_USING_STM32F7
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bool "STM32F7"
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config MR_USING_STM32G0
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bool "STM32G0"
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config MR_USING_STM32G4
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bool "STM32G4"
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config MR_USING_STM32H5
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bool "STM32H5"
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config MR_USING_STM32H7
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bool "STM32H7"
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config MR_USING_STM32L0
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bool "STM32L0"
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config MR_USING_STM32L1
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bool "STM32L1"
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config MR_USING_STM32L4
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bool "STM32L4"
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config MR_USING_STM32L5
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bool "STM32L5"
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endchoice
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menu "ADC"
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config MR_USING_ADC1
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bool "Enable ADC1 driver"
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default n
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config MR_USING_ADC2
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bool "Enable ADC2 driver"
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default n
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config MR_USING_ADC3
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bool "Enable ADC3 driver"
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default n
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endmenu
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menu "GPIO"
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config MR_USING_GPIOA
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bool "Enable GPIOA driver"
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default n
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@@ -21,11 +81,9 @@ menu "Board configure"
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config MR_USING_GPIOE
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bool "Enable GPIOE driver"
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default n
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endmenu
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menu "UART"
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config MR_USING_UART1
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bool "Enable UART1 driver"
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default n
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@@ -57,11 +115,9 @@ menu "Board configure"
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config MR_USING_UART8
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bool "Enable UART8 driver"
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default n
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endmenu
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menu "SPI"
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config MR_USING_SPI1
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bool "Enable SPI1 driver"
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default n
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@@ -85,7 +141,6 @@ menu "Board configure"
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config MR_USING_SPI6
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bool "Enable SPI6 driver"
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default n
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endmenu
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menu "Timer"
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191
bsp/st/driver/drv_adc.c
Normal file
191
bsp/st/driver/drv_adc.c
Normal file
@@ -0,0 +1,191 @@
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/*
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* @copyright (c) 2023, MR Development Team
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*
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* @license SPDX-License-Identifier: Apache-2.0
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*
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* @date 2023-11-11 MacRsh First version
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*/
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#include "drv_adc.h"
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#ifdef MR_USING_ADC
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#if !defined(MR_USING_ADC1) && !defined(MR_USING_ADC2) && !defined(MR_USING_ADC3)
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#error "Please define at least one ADC macro like MR_USING_ADC1. Otherwise undefine MR_USING_ADC."
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#else
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enum drv_adc_index
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{
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#ifdef MR_USING_ADC1
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DRV_INDEX_ADC1,
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#endif /* MR_USING_ADC1 */
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#ifdef MR_USING_ADC2
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DRV_INDEX_ADC2,
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#endif /* MR_USING_ADC2 */
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#ifdef MR_USING_ADC3
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DRV_INDEX_ADC3,
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#endif /* MR_USING_ADC3 */
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};
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static const char *adc_name[] =
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{
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#ifdef MR_USING_ADC1
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"adc1",
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#endif /* MR_USING_ADC1 */
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#ifdef MR_USING_ADC2
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"adc2",
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#endif /* MR_USING_ADC2 */
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#ifdef MR_USING_ADC3
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"adc3",
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#endif /* MR_USING_ADC3 */
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};
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static struct drv_adc_data adc_drv_data[] =
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{
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#ifdef MR_USING_ADC1
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{{0}, ADC1},
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#endif /* MR_USING_ADC1 */
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#ifdef MR_USING_ADC2
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{{0}, ADC2},
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#endif /* MR_USING_ADC2 */
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#ifdef MR_USING_ADC3
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{{0}, ADC3},
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#endif /* MR_USING_ADC3 */
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};
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static struct drv_adc_channel_data adc_channel_drv_data[] =
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{
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{ADC_CHANNEL_0},
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{ADC_CHANNEL_1},
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{ADC_CHANNEL_2},
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{ADC_CHANNEL_3},
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{ADC_CHANNEL_4},
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{ADC_CHANNEL_5},
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{ADC_CHANNEL_6},
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{ADC_CHANNEL_7},
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{ADC_CHANNEL_8},
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{ADC_CHANNEL_9},
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{ADC_CHANNEL_10},
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{ADC_CHANNEL_11},
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{ADC_CHANNEL_12},
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{ADC_CHANNEL_13},
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{ADC_CHANNEL_14},
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{ADC_CHANNEL_15},
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{ADC_CHANNEL_16},
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{ADC_CHANNEL_17},
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};
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static struct mr_adc adc_dev[mr_array_num(adc_drv_data)];
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static struct drv_adc_channel_data *drv_adc_get_channel_data(int channel)
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{
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if (channel >= mr_array_num(adc_channel_drv_data))
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{
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return NULL;
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}
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return &adc_channel_drv_data[channel];
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}
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static int drv_adc_configure(struct mr_adc *adc, int state)
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{
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struct drv_adc_data *adc_data = (struct drv_adc_data *)adc->dev.drv->data;
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adc_data->handle.Instance = adc_data->instance;
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if (state == ENABLE)
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{
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/* Configure ADC */
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adc_data->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
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adc_data->handle.Init.Resolution = ADC_RESOLUTION_12B;
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adc_data->handle.Init.ScanConvMode = DISABLE;
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adc_data->handle.Init.ContinuousConvMode = DISABLE;
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adc_data->handle.Init.DiscontinuousConvMode = DISABLE;
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adc_data->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
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adc_data->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START;
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adc_data->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
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adc_data->handle.Init.NbrOfConversion = 1;
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adc_data->handle.Init.DMAContinuousRequests = DISABLE;
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adc_data->handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
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HAL_ADC_Init(&adc_data->handle);
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} else
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{
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/* Configure ADC */
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HAL_ADC_DeInit(&adc_data->handle);
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}
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return MR_EOK;
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}
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static int drv_adc_channel_configure(struct mr_adc *adc, int channel, int state)
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{
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return MR_EOK;
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}
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static uint32_t drv_adc_read(struct mr_adc *adc, int channel)
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{
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struct drv_adc_data *adc_data = (struct drv_adc_data *)adc->dev.drv->data;
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struct drv_adc_channel_data *adc_channel_data = drv_adc_get_channel_data(channel);
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ADC_ChannelConfTypeDef sConfig = {0};
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/* Check channel is valid */
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if (adc_channel_data == NULL)
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{
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return 0;
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}
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/* Read data */
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sConfig.Channel = adc_channel_data->channel;
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sConfig.Rank = 1;
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sConfig.SamplingTime = ADC_SAMPLETIME_56CYCLES;
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HAL_ADC_ConfigChannel(&adc_data->handle, &sConfig);
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HAL_ADC_Start(&adc_data->handle);
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HAL_ADC_PollForConversion(&adc_data->handle, INT16_MAX);
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HAL_ADC_Stop(&adc_data->handle);
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return HAL_ADC_GetValue(&adc_data->handle);
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}
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static struct mr_adc_ops adc_drv_ops =
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{
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drv_adc_configure,
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drv_adc_channel_configure,
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drv_adc_read
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};
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static struct mr_drv adc_drv[] =
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{
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#ifdef MR_USING_ADC1
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{
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Mr_Drv_Type_ADC,
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&adc_drv_ops,
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&adc_drv_data[DRV_INDEX_ADC1],
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},
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#endif /* MR_USING_ADC1 */
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#ifdef MR_USING_ADC2
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{
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Mr_Drv_Type_ADC,
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&adc_drv_ops,
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&adc_drv_data[DRV_INDEX_ADC2],
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},
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#endif /* MR_USING_ADC2 */
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#ifdef MR_USING_ADC3
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{
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Mr_Drv_Type_ADC,
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&adc_drv_ops,
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&adc_drv_data[DRV_INDEX_ADC3],
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},
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#endif /* MR_USING_ADC3 */
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};
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int drv_adc_init(void)
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{
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int index = 0;
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for (index = 0; index < mr_array_num(adc_dev); index++)
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{
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mr_adc_register(&adc_dev[index], adc_name[index], &adc_drv[index]);
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}
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return MR_EOK;
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}
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MR_DRV_EXPORT(drv_adc_init);
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#endif /* !defined(MR_USING_ADC1) && !defined(MR_USING_ADC2) && !defined(MR_USING_ADC3) */
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#endif /* MR_USING_ADC */
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38
bsp/st/driver/drv_adc.h
Normal file
38
bsp/st/driver/drv_adc.h
Normal file
@@ -0,0 +1,38 @@
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/*
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* @copyright (c) 2023, MR Development Team
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*
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* @license SPDX-License-Identifier: Apache-2.0
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*
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* @date 2023-11-11 MacRsh First version
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*/
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#ifndef _DRV_ADC_H_
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#define _DRV_ADC_H_
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#include "include/device/adc.h"
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#include "mr_board.h"
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifdef MR_USING_ADC
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struct drv_adc_data
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{
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ADC_HandleTypeDef *handle;
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ADC_TypeDef *instance;
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};
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struct drv_adc_channel_data
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{
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uint32_t channel;
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};
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#endif /* MR_USING_ADC */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* _DRV_ADC_H_ */
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@@ -137,7 +137,7 @@ static uint32_t drv_adc_read(struct mr_adc *adc, int channel)
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/* Check channel is valid */
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if (adc_channel_data == NULL)
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{
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return MR_EINVAL;
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return 0;
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}
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/* Read data */
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