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1.优化命令结构。

Browse Source 
2.框架与驱动解耦。
This commit is contained in:
MacRsh
2023-12-01 21:59:47 +08:00
parent 7d0eb9b986
commit d7a781c1dd
15 changed files with 106 additions and 81 deletions
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2
bsp/wch/ch32v30x/driver/drv_pin.c
View File

@@ -233,7 +233,7 @@ static int drv_pin_configure(struct mr_pin *pin, int number, int mode)
default:
{
break;
return MR_EINVAL;
}
}

2
device/timer.c
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@@ -15,7 +15,7 @@ static int timer_calculate(struct mr_timer *timer, uint32_t timeout)
uint32_t clk = timer->info->clk, psc_max = timer->info->prescaler_max, per_max = timer->info->period_max;
uint32_t psc_best = 0, per_best = 0, reload_best = 0;
uint32_t psc = 0, per = 0, reload = 0;
int error = 0, error_min = INT_MAX;
int error = 0, error_min = INT32_MAX;
/* Check the clock */
if (clk == 0)

8
include/device/adc.h
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@@ -23,17 +23,13 @@ extern "C" {
#define MR_ADC_STATE_DISABLE MR_DISABLE /**< ADC disabled */
#define MR_ADC_STATE_ENABLE MR_ENABLE /**< ADC enabled */
/**
* @brief ADC channel state command.
*/
#define MR_CTL_ADC_SET_CHANNEL_STATE ((0x01|0x80) << 16) /**< Set channel state */
#define MR_CTL_ADC_GET_CHANNEL_STATE ((0x01|0x00) << 16) /**< Get channel state */
/**
* @brief ADC control command.
*/
#define MR_CTL_ADC_SET_CHANNEL MR_CTL_SET_OFFSET /**< Set channel */
#define MR_CTL_ADC_GET_CHANNEL MR_CTL_GET_OFFSET /**< Get channel */
#define MR_CTL_ADC_SET_CHANNEL_STATE (0x01 << 8) /**< Set channel state */
#define MR_CTL_ADC_GET_CHANNEL_STATE (-(0x01 << 8)) /**< Get channel state */
/**
* @brief ADC data type.

4
include/device/can.h
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@@ -54,8 +54,8 @@ struct mr_can_config
* @brief CAN control command.
*/
#define MR_CTL_CAN_SET_ID MR_CTL_SET_OFFSET /**< Set id */
#define MR_CTL_CAN_SET_RD_CALL MR_CTL_SET_RD_CALL /**< Set read call */
#define MR_CTL_CAN_GET_ID MR_CTL_GET_OFFSET /**< Get id */
#define MR_CTL_CAN_SET_RD_CALL MR_CTL_SET_RD_CALL /**< Set read call */
#define MR_CTL_CAN_GET_RD_CALL MR_CTL_GET_RD_CALL /**< Get read call */
/**
@@ -66,7 +66,7 @@ typedef uint8_t mr_can_data_t; /**< CAN rea
/**
* @brief CAN ISR events.
*/
#define MR_ISR_CAN_RD_INT (MR_ISR_RD | (0x01 << 16)) /**< Read interrupt */
#define MR_ISR_CAN_RD_INT (MR_ISR_RD | (0x01 << 8)) /**< Read interrupt */
/**
* @brief CAN bus structure.

8
include/device/dac.h
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@@ -23,17 +23,13 @@ extern "C" {
#define MR_DAC_STATE_DISABLE MR_DISABLE /**< DAC disabled */
#define MR_DAC_STATE_ENABLE MR_ENABLE /**< DAC enabled */
/**
* @brief DAC channel state command.
*/
#define MR_CTL_DAC_SET_CHANNEL_STATE ((0x01|0x80) << 16) /**< Set channel state */
#define MR_CTL_DAC_GET_CHANNEL_STATE ((0x01|0x00) << 16) /**< Get channel state */
/**
* @brief DAC control command.
*/
#define MR_CTL_DAC_SET_CHANNEL MR_CTL_SET_OFFSET /**< Set channel */
#define MR_CTL_DAC_GET_CHANNEL MR_CTL_GET_OFFSET /**< Get channel */
#define MR_CTL_DAC_SET_CHANNEL_STATE (0x01 << 8) /**< Set channel state */
#define MR_CTL_DAC_GET_CHANNEL_STATE (-(0x01 << 8)) /**< Get channel state */
/**
* @brief DAC data type.

4
include/device/i2c.h
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@@ -55,8 +55,8 @@ struct mr_i2c_config
* @brief I2C control command.
*/
#define MR_CTL_I2C_SET_REG MR_CTL_SET_OFFSET /**< Set register */
#define MR_CTL_I2C_SET_RD_CALL MR_CTL_SET_RD_CALL /**< Set read callback */
#define MR_CTL_I2C_GET_REG MR_CTL_GET_OFFSET /**< Get register */
#define MR_CTL_I2C_SET_RD_CALL MR_CTL_SET_RD_CALL /**< Set read callback */
#define MR_CTL_I2C_GET_RD_CALL MR_CTL_GET_RD_CALL /**< Get read callback */
/**
@@ -67,7 +67,7 @@ typedef uint8_t mr_i2c_data_t; /**< I2C rea
/**
* @brief I2C ISR events.
*/
#define MR_ISR_I2C_RD_INT (MR_ISR_RD | (0x01 << 16)) /**< Read interrupt */
#define MR_ISR_I2C_RD_INT (MR_ISR_RD | (0x01 << 8)) /**< Read interrupt */
/**
* @brief I2C bus structure.

8
include/device/pin.h
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@@ -45,21 +45,21 @@ extern "C" {
/**
* @brief PIN control command.
*/
#define MR_CTL_PIN_SET_MODE ((0x01|0x80) << 16) /**< Set pin mode */
#define MR_CTL_PIN_SET_NUMBER MR_CTL_SET_OFFSET /**< Set pin number */
#define MR_CTL_PIN_SET_EXTI_CALL MR_CTL_SET_RD_CALL /**< Set pin exti callback */
#define MR_CTL_PIN_GET_NUMBER MR_CTL_GET_OFFSET /**< Get pin number */
#define MR_CTL_PIN_SET_EXTI_CALL MR_CTL_SET_RD_CALL /**< Set pin exti callback */
#define MR_CTL_PIN_GET_EXTI_CALL MR_CTL_GET_RD_CALL /**< Get pin exti callback */
#define MR_CTL_PIN_SET_MODE (0x01 << 8) /**< Set pin mode */
/**
* @brief PIN data type.
*/
typedef uint8_t mr_pin_data_t; /**< PIN read/write data type */
typedef uint8_t mr_pin_data_t; /**< PIN read/write data type */
/**
* @brief PIN ISR events.
*/
#define MR_ISR_PIN_RD_INT (MR_ISR_RD | (0x01 << 16)) /**< Read interrupt */
#define MR_ISR_PIN_RD_INT (MR_ISR_RD | (0x01 << 8)) /**< Read interrupt */
/**
* @brief PIN structure.

6
include/device/serial.h
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@@ -83,8 +83,8 @@ struct mr_serial_config
* @brief SERIAL control command.
*/
#define MR_CTL_SERIAL_SET_RD_CALL MR_CTL_SET_RD_CALL /**< Set read callback */
#define MR_CTL_SERIAL_SET_WR_CALL MR_CTL_SET_WR_CALL /**< Set write complete callback */
#define MR_CTL_SERIAL_GET_RD_CALL MR_CTL_GET_RD_CALL /**< Get read callback */
#define MR_CTL_SERIAL_SET_WR_CALL MR_CTL_SET_WR_CALL /**< Set write complete callback */
#define MR_CTL_SERIAL_GET_WR_CALL MR_CTL_GET_WR_CALL /**< Get write complete callback */
/**
@@ -95,8 +95,8 @@ typedef uint8_t mr_serial_data_t; /**< SERIAL
/**
* @brief SERIAL ISR events.
*/
#define MR_ISR_SERIAL_RD_INT (MR_ISR_RD | (0x01 << 16)) /**< Read interrupt */
#define MR_ISR_SERIAL_WR_INT (MR_ISR_WR | (0x02 << 16)) /**< Write interrupt */
#define MR_ISR_SERIAL_RD_INT (MR_ISR_RD | (0x01 << 8)) /**< Read interrupt */
#define MR_ISR_SERIAL_WR_INT (MR_ISR_WR | (0x02 << 8)) /**< Write interrupt */
/**
* @brief SERIAL structure.

6
include/device/spi.h
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@@ -92,10 +92,10 @@ struct mr_spi_transfer
* @brief SPI control command.
*/
#define MR_CTL_SPI_SET_REG MR_CTL_SET_OFFSET /**< Set register */
#define MR_CTL_SPI_TRANSFER ((0x01|0x80) << 16) /**< Transfer */
#define MR_CTL_SPI_RD_CALL MR_CTL_SET_RD_CALL /**< Set read callback */
#define MR_CTL_SPI_GET_REG MR_CTL_GET_OFFSET /**< Get register */
#define MR_CTL_SPI_SET_RD_CALL MR_CTL_SET_RD_CALL /**< Set read callback */
#define MR_CTL_SPI_GET_RD_CALL MR_CTL_GET_RD_CALL /**< Get read callback */
#define MR_CTL_SPI_TRANSFER (0x01 << 8) /**< Transfer */
/**
* @brief SPI data type.
@@ -105,7 +105,7 @@ typedef uint8_t mr_spi_data_t; /**< SPI rea
/**
* @brief SPI ISR events.
*/
#define MR_ISR_SPI_RD_INT (MR_ISR_RD | (0x01 << 16)) /**< Read interrupt */
#define MR_ISR_SPI_RD_INT (MR_ISR_RD | (0x01 << 8)) /**< Read interrupt */
/**
* @brief SPI bus structure.

6
include/mr_api.h
View File

@@ -60,8 +60,8 @@ const char *mr_strerror(int err);
*/
int mr_dev_register(struct mr_dev *dev,
const char *name,
uint32_t type,
uint32_t sflags,
int type,
int sflags,
struct mr_dev_ops *ops,
struct mr_drv *drv);
void mr_dev_isr(struct mr_dev *dev, int event, void *args);
@@ -72,7 +72,7 @@ int mr_dev_get_full_name(struct mr_dev *dev, char *buf, size_t bufsz);
* @addtogroup Device description.
* @{
*/
int mr_dev_open(const char *name, uint32_t oflags);
int mr_dev_open(const char *name, int oflags);
int mr_dev_close(int desc);
ssize_t mr_dev_read(int desc, void *buf, size_t size);
ssize_t mr_dev_write(int desc, const void *buf, size_t size);

76
include/mr_def.h
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@@ -117,12 +117,6 @@ typedef int (*mr_init_fn_t)(void);
#define MR_FALSE (0) /**< False */
#define MR_TRUE (1) /**< True */
/**
* @brief Max/min value.
*/
#define INT_MAX (0x7fffffff) /**< Max int value */
#define INT_MIN (-0x7fffffff) /**< Min int value */
/**
* @brief Double linked list structure.
*/
@@ -214,21 +208,21 @@ struct mr_dev;
/**
* @brief Lock flags.
*/
#define MR_LFLAG_RD ((0x01) << 24) /**< Read lock */
#define MR_LFLAG_WR ((0x02) << 24) /**< Write lock */
#define MR_LFLAG_RDWR ((0x03) << 24) /**< Read/write lock */
#define MR_LFLAG_NONBLOCK ((0x04) << 24) /**< Non-blocking lock */
#define MR_LFLAG_SLEEP ((0x08) << 24) /**< Sleep lock */
#define MR_LFLAG_RD (0x01) /**< Read lock */
#define MR_LFLAG_WR (0x02) /**< Write lock */
#define MR_LFLAG_RDWR (0x03) /**< Read/write lock */
#define MR_LFLAG_NONBLOCK (0x04) /**< Non-blocking lock */
#define MR_LFLAG_SLEEP (0x08) /**< Sleep lock */
/**
* @brief Open flags.
*/
#define MR_OFLAG_CLOSED (0) /**< Closed */
#define MR_OFLAG_RDONLY ((0x01) << 24) /**< Read only */
#define MR_OFLAG_WRONLY ((0x02) << 24) /**< Write only */
#define MR_OFLAG_RDWR ((0x03) << 24) /**< Read/write */
#define MR_OFLAG_NONBLOCK ((0x04) << 24) /**< Non-blocking */
#define MR_OFLAG_DMA ((0x08) << 24) /**< DMA */
#define MR_OFLAG_RDONLY (0x01) /**< Read only */
#define MR_OFLAG_WRONLY (0x02) /**< Write only */
#define MR_OFLAG_RDWR (0x03) /**< Read/write */
#define MR_OFLAG_NONBLOCK (0x04) /**< Non-blocking */
#define MR_OFLAG_DMA (0x08) /**< DMA */
/**
* @brief Support flags.
@@ -239,36 +233,36 @@ struct mr_dev;
#define MR_SFLAG_RDWR MR_OFLAG_RDWR /**< Read/write */
#define MR_SFLAG_NONBLOCK MR_OFLAG_NONBLOCK /**< Non-blocking */
#define MR_SFLAG_DMA MR_OFLAG_DMA /**< DMA */
#define MR_SFLAG_NONDRV ((0x10) << 24) /**< Non-driver */
#define MR_SFLAG_ONLY ((0x20) << 24) /**< Only */
#define MR_SFLAG_NONDRV (0x10) /**< Non-driver */
#define MR_SFLAG_ONLY (0x20) /**< Only */
/**
* @brief Descriptor control command.
*/
#define MR_CTL_SET_OFFSET ((0x01|0x80) << 24) /**< Set offset */
#define MR_CTL_SET_RD_CALL ((0x02|0x80) << 24) /**< Set read callback */
#define MR_CTL_SET_WR_CALL ((0x03|0x80) << 24) /**< Set write callback */
#define MR_CTL_SET_SLEEP ((0x04|0x80) << 24) /**< Set sleep */
#define MR_CTL_SET_WAKEUP ((0x05|0x80) << 24) /**< Set wakeup */
#define MR_CTL_SET_CONFIG ((0x06|0x80) << 24) /**< Set configuration */
#define MR_CTL_SET_RD_BUFSZ ((0x07|0x80) << 24) /**< Set read buffer size */
#define MR_CTL_SET_WR_BUFSZ ((0x08|0x80) << 24) /**< Set write buffer size */
#define MR_CTL_SET_OFFSET (0x01) /**< Set offset */
#define MR_CTL_SET_RD_CALL (0x02) /**< Set read callback */
#define MR_CTL_SET_WR_CALL (0x03) /**< Set write callback */
#define MR_CTL_SET_SLEEP (0x04) /**< Set sleep */
#define MR_CTL_SET_WAKEUP (0x05) /**< Set wakeup */
#define MR_CTL_SET_CONFIG (0x06) /**< Set configuration */
#define MR_CTL_SET_RD_BUFSZ (0x07) /**< Set read buffer size */
#define MR_CTL_SET_WR_BUFSZ (0x08) /**< Set write buffer size */
#define MR_CTL_GET_OFFSET ((0x01|0x00) << 24) /**< Get offset */
#define MR_CTL_GET_RD_CALL ((0x02|0x00) << 24) /**< Get read callback */
#define MR_CTL_GET_WR_CALL ((0x03|0x00) << 24) /**< Get write callback */
#define MR_CTL_GET_SLEEP ((0x04|0x00) << 24) /**< Get sleep (reserved) */
#define MR_CTL_GET_WAKEUP ((0x05|0x00) << 24) /**< Get wakeup (reserved) */
#define MR_CTL_GET_CONFIG ((0x06|0x00) << 24) /**< Get configuration */
#define MR_CTL_GET_RD_BUFSZ ((0x07|0x00) << 24) /**< Get read buffer size */
#define MR_CTL_GET_WR_BUFSZ ((0x08|0x00) << 24) /**< Get write buffer size */
#define MR_CTL_GET_OFFSET (-(0x01)) /**< Get offset */
#define MR_CTL_GET_RD_CALL (-(0x02)) /**< Get read callback */
#define MR_CTL_GET_WR_CALL (-(0x03)) /**< Get write callback */
#define MR_CTL_GET_SLEEP (-(0x04)) /**< Get sleep (reserved) */
#define MR_CTL_GET_WAKEUP (-(0x05)) /**< Get wakeup (reserved) */
#define MR_CTL_GET_CONFIG (-(0x06)) /**< Get configuration */
#define MR_CTL_GET_RD_BUFSZ (-(0x07)) /**< Get read buffer size */
#define MR_CTL_GET_WR_BUFSZ (-(0x08)) /**< Get write buffer size */
/**
* @brief ISR event.
*/
#define MR_ISR_RD ((0x01) << 24) /**< Read interrupt */
#define MR_ISR_WR ((0x02) << 24) /**< Write interrupt */
#define MR_ISR_MASK ((0xff) << 24) /**< Interrupt mask */
#define MR_ISR_RD (0x01) /**< Read interrupt */
#define MR_ISR_WR (0x02) /**< Write interrupt */
#define MR_ISR_MASK (0xff) /**< Interrupt mask */
/**
* @brief Device operations structure.
@@ -288,7 +282,7 @@ struct mr_dev_ops
*/
struct mr_dev
{
uint32_t magic; /**< Magic number */
int magic; /**< Magic number */
#ifndef MR_CFG_NAME_MAX
#define MR_CFG_NAME_MAX (8)
#endif /* MR_CFG_NAME_MAX */
@@ -297,11 +291,11 @@ struct mr_dev
struct mr_list slist; /**< Slave list */
void *link; /**< Link */
uint32_t type; /**< Device type */
int type; /**< Device type */
size_t ref_count; /**< Reference count */
#ifdef MR_USING_RDWR_CTL
uint32_t sflags; /**< Support flags */
volatile uint32_t lflags; /**< Lock flags */
int sflags; /**< Support flags */
volatile int lflags; /**< Lock flags */
#endif /* MR_USING_RDWR_CTL */
struct

41
include/mr_lib.h
View File

@@ -10,6 +10,45 @@
#define _MR_LIB_H_
#include "mr_api.h"
#include "mr_drv.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifdef MR_USING_ADC
#include "device/adc.h"
#endif
#ifdef MR_USING_CAN
#include "device/can.h"
#endif
#ifdef MR_USING_DAC
#include "device/dac.h"
#endif
#ifdef MR_USING_I2C
#include "device/i2c.h"
#endif
#ifdef MR_USING_PIN
#include "device/pin.h"
#endif
#ifdef MR_USING_SERIAL
#include "device/serial.h"
#endif
#ifdef MR_USING_SPI
#include "device/spi.h"
#endif
#ifdef MR_USING_TIMER
#include "device/timer.h"
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _MR_LIB_H_ */

2
module/icm20602/icm20602.c
View File

@@ -297,4 +297,4 @@ int mr_icm20602_register(struct mr_icm20602 *icm20602, const char *name, int cs_
return mr_dev_register(&icm20602->dev, name, Mr_Dev_Type_Sensor, MR_SFLAG_RDONLY | MR_SFLAG_NONDRV, &ops, MR_NULL);
}
#endif /* MR_USING_ICM20602 */
#endif /* MR_USING_ICM20602 */

10
source/device.c
View File

@@ -177,7 +177,7 @@ MR_INLINE int dev_register(struct mr_dev *dev, const char *name)
return MR_EINVAL;
}
MR_INLINE int dev_open(struct mr_dev *dev, uint32_t oflags)
MR_INLINE int dev_open(struct mr_dev *dev, int oflags)
{
#ifdef MR_USING_RDWR_CTL
if (mr_bits_is_set(dev->sflags, oflags) != MR_ENABLE)
@@ -390,8 +390,8 @@ static int dev_ioctl(struct mr_dev *dev, int desc, int off, int cmd, void *args)
*/
int mr_dev_register(struct mr_dev *dev,
const char *name,
uint32_t type,
uint32_t sflags,
int type,
int sflags,
struct mr_dev_ops *ops,
struct mr_drv *drv)
{
@@ -528,7 +528,7 @@ int mr_dev_get_full_name(struct mr_dev *dev, char *buf, size_t bufsz)
static struct mr_desc
{
struct mr_dev *dev; /* Device */
uint32_t oflags; /* Open flags */
int oflags; /* Open flags */
int offset; /* Offset */
#ifndef MR_CFG_DESC_MAX
#define MR_CFG_DESC_MAX (32)
@@ -588,7 +588,7 @@ static void desc_free(int desc)
*
* @return The descriptor of the device, otherwise an error code.
*/
int mr_dev_open(const char *name, uint32_t oflags)
int mr_dev_open(const char *name, int oflags)
{
mr_assert(name != MR_NULL);
mr_assert(oflags != MR_OFLAG_CLOSED);

4
source/service.c
View File

@@ -178,7 +178,7 @@ MR_WEAK void *mr_malloc(size_t size)
block_prev->next = block->next;
/* Allocate memory */
memory = (void *)((uint8_t *)block) + sizeof(struct mr_heap_block);
memory = (void *)((uint8_t *)block + sizeof(struct mr_heap_block));
residual = block->size - size;
/* Set the block information */
@@ -312,7 +312,7 @@ MR_WEAK int mr_printf_output(const char *buf, size_t size)
int mr_printf(const char *fmt, ...)
{
char buf[128] = {0};
va_list args = MR_NULL;
va_list args;
va_start(args, fmt);
int ret = vsnprintf(buf, sizeof(buf) - 1, fmt, args);