1.新增CH32V203系列驱动。
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MacRsh
149
bsp/wch/ch32v203/driver/Kconfig
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149
bsp/wch/ch32v203/driver/Kconfig
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menu "Driver configure"
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config MR_USING_CH32V20X
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bool "Enable CH32V20X driver"
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default y
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menu "ADC"
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config MR_USING_ADC1
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bool "Enable ADC1 driver"
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default n
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config MR_USING_ADC2
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bool "Enable ADC2 driver"
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default n
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endmenu
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menu "I2C"
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config MR_USING_I2C1
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bool "Enable I2C1 driver"
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default n
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menu "I2C1 driver configure"
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depends on MR_USING_I2C1
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config MR_CFG_I2C1_GROUP
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int "I2C1 Group"
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default 1
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range 1 2
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endmenu
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config MR_USING_I2C2
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bool "Enable I2C2 driver"
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default n
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menu "I2C2 driver configure"
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depends on MR_USING_I2C2
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config MR_CFG_I2C2_GROUP
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int "I2C2 Group"
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default 1
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range 1 1
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endmenu
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endmenu
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menu "UART"
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config MR_USING_UART1
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bool "Enable UART1 driver"
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default n
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menu "UART1 driver configure"
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depends on MR_USING_UART1
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config MR_CFG_UART1_GROUP
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int "UART1 Group"
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default 1
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range 1 2
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endmenu
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config MR_USING_UART2
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bool "Enable UART2 driver"
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default n
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menu "UART2 driver configure"
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depends on MR_USING_UART2
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config MR_CFG_UART2_GROUP
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int "UART2 Group"
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default 1
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range 1 1
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endmenu
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config MR_USING_UART3
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bool "Enable UART3 driver"
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default n
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menu "UART3 driver configure"
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depends on MR_USING_UART3
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config MR_CFG_UART3_GROUP
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int "UART3 Group"
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default 1
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range 1 2
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endmenu
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config MR_USING_UART4
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bool "Enable UART4 driver"
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default n
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menu "UART4 driver configure"
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depends on MR_USING_UART4
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config MR_CFG_UART4_GROUP
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int "UART4 Group"
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default 1
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range 1 2
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endmenu
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endmenu
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menu "SPI"
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config MR_USING_SPI1
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bool "Enable SPI1 driver"
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default n
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menu "SPI1 driver configure"
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depends on MR_USING_SPI1
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config MR_CFG_SPI1_GROUP
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int "SPI1 Group"
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default 1
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range 1 2
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endmenu
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config MR_USING_SPI2
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bool "Enable SPI2 driver"
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default n
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menu "SPI2 driver configure"
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depends on MR_USING_SPI2
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config MR_CFG_SPI2_GROUP
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int "SPI2 Group"
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default 1
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range 1 1
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endmenu
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endmenu
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menu "Timer"
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config MR_USING_TIMER1
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bool "Enable Timer1 driver"
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default n
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config MR_USING_TIMER2
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bool "Enable Timer2 driver"
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default n
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config MR_USING_TIMER3
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bool "Enable Timer3 driver"
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default n
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config MR_USING_TIMER4
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bool "Enable Timer4 driver"
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default n
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config MR_USING_TIMER5
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bool "Enable Timer5 driver"
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default n
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endmenu
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endmenu
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162
bsp/wch/ch32v203/driver/mr_board.h
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162
bsp/wch/ch32v203/driver/mr_board.h
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/*
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* @copyright (c) 2023-2024, MR Development Team
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*
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* @license SPDX-License-Identifier: Apache-2.0
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*
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* @date 2023-11-10 MacRsh First version
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*/
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#ifndef _MR_BOARD_H_
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#define _MR_BOARD_H_
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#include "ch32v20x.h"
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#define DRV_ADC_CHANNEL_CONFIG \
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{ \
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{ADC_Channel_0, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_0}, \
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{ADC_Channel_1, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_1}, \
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{ADC_Channel_2, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_2}, \
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{ADC_Channel_3, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_3}, \
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{ADC_Channel_4, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_4}, \
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{ADC_Channel_5, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_5}, \
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{ADC_Channel_6, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_6}, \
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{ADC_Channel_7, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_7}, \
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{ADC_Channel_8, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_0}, \
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{ADC_Channel_9, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_1}, \
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{ADC_Channel_10, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_0}, \
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{ADC_Channel_11, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_1}, \
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{ADC_Channel_12, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_2}, \
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{ADC_Channel_13, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_3}, \
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{ADC_Channel_14, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_4}, \
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{ADC_Channel_15, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_5}, \
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{ADC_Channel_16, 0, NULL, 0}, \
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{ADC_Channel_17, 0, NULL, 0}, \
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}
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#if (MR_CFG_I2C1_GROUP == 1)
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#define DRV_I2C1_CONFIG \
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{I2C1, RCC_APB1Periph_I2C1, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_6, GPIOB, GPIO_Pin_7, I2C1_EV_IRQn, 0}
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#elif (MR_CFG_I2C1_GROUP == 2)
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#define DRV_I2C1_CONFIG \
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{I2C1, RCC_APB1Periph_I2C1, RCC_APB2Periph_GPIOD, GPIOB, GPIO_Pin_8, GPIOB, GPIO_Pin_9, I2C1_EV_IRQn, GPIO_Remap_I2C1}
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#endif /* MR_CFG_I2C1_GROUP */
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#if (MR_CFG_I2C2_GROUP == 1)
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#define DRV_I2C2_CONFIG \
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{I2C2, RCC_APB1Periph_I2C2, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_10, GPIOB, GPIO_Pin_11, I2C2_EV_IRQn, 0}
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#endif /* MR_CFG_I2C2_GROUP */
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#define DRV_PIN_IRQ_MAP_CONFIG \
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{ \
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EXTI0_IRQn, \
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EXTI1_IRQn, \
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EXTI2_IRQn, \
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EXTI3_IRQn, \
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EXTI4_IRQn, \
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EXTI9_5_IRQn, \
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EXTI9_5_IRQn, \
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EXTI9_5_IRQn, \
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EXTI9_5_IRQn, \
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EXTI9_5_IRQn, \
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EXTI15_10_IRQn, \
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EXTI15_10_IRQn, \
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EXTI15_10_IRQn, \
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EXTI15_10_IRQn, \
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EXTI15_10_IRQn, \
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EXTI15_10_IRQn, \
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}
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#define DRV_PIN_PORT_CONFIG \
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{ \
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GPIOA, \
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GPIOB, \
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GPIOC, \
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GPIOD, \
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}
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#define DRV_PIN_CONFIG \
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{ \
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GPIO_Pin_0, \
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GPIO_Pin_1, \
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GPIO_Pin_2, \
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GPIO_Pin_3, \
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GPIO_Pin_4, \
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GPIO_Pin_5, \
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GPIO_Pin_6, \
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GPIO_Pin_7, \
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GPIO_Pin_8, \
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GPIO_Pin_9, \
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GPIO_Pin_10, \
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GPIO_Pin_11, \
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GPIO_Pin_12, \
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GPIO_Pin_13, \
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GPIO_Pin_14, \
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GPIO_Pin_15, \
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}
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#if (MR_CFG_UART1_GROUP == 1)
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#define DRV_UART1_CONFIG \
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{USART1, RCC_APB2Periph_USART1, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_10, GPIOA, GPIO_Pin_9, USART1_IRQn, 0}
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#elif (MR_CFG_UART1_GROUP == 2)
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#define DRV_UART1_CONFIG \
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{USART1, RCC_APB2Periph_USART1, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_7, GPIOB, GPIO_Pin_6, USART1_IRQn, GPIO_Remap_USART1}
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#endif /* MR_CFG_UART1_GROUP */
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#if (MR_CFG_UART2_GROUP == 1)
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#define DRV_UART2_CONFIG \
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{USART2, RCC_APB1Periph_USART2, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_3, GPIOA, GPIO_Pin_2, USART2_IRQn, 0}
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#endif /* MR_CFG_UART2_GROUP */
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#if (MR_CFG_UART3_GROUP == 1)
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#define DRV_UART3_CONFIG \
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{USART3, RCC_APB1Periph_USART3, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_11, GPIOB, GPIO_Pin_10, USART3_IRQn, 0}
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#elif (MR_CFG_UART3_GROUP == 2)
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#define DRV_UART3_CONFIG \
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{USART3, RCC_APB1Periph_USART3, RCC_APB2Periph_GPIOC, GPIOC, GPIO_Pin_11, GPIOC, GPIO_Pin_10, USART3_IRQn, GPIO_PartialRemap_USART3}
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#endif /* MR_CFG_UART3_GROUP */
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#if (MR_CFG_UART4_GROUP == 1)
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#define DRV_UART4_CONFIG \
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{UART4, RCC_APB1Periph_UART4, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_1, GPIOB, GPIO_Pin_0, UART4_IRQn, 0}
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#elif (MR_CFG_UART4_GROUP == 2)
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#define DRV_UART4_CONFIG \
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{UART4, RCC_APB1Periph_UART4, RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_5, GPIOA, GPIO_Pin_5, UART4_IRQn, GPIO_PartialRemap_USART4}
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#endif /* MR_CFG_UART4_GROUP */
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#if (MR_CFG_SPI1_GROUP == 1)
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#define DRV_SPI1_CONFIG \
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{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOA, GPIOA, GPIO_Pin_5, GPIOA, GPIO_Pin_6, GPIOA, GPIO_Pin_7, SPI1_IRQn, 0}
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#elif (MR_CFG_SPI1_GROUP == 2)
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#define DRV_SPI1_CONFIG \
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{SPI1, RCC_APB2Periph_SPI1, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_3, GPIOB, GPIO_Pin_4, GPIOB, GPIO_Pin_5, SPI1_IRQn, GPIO_Remap_SPI1}
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#endif /* MR_CFG_SPI1_GROUP */
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#define DRV_SPI2_CONFIG \
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{SPI2, RCC_APB1Periph_SPI2, RCC_APB2Periph_GPIOB, GPIOB, GPIO_Pin_13, GPIOB, GPIO_Pin_14, GPIOB, GPIO_Pin_15, SPI2_IRQn, 0}
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#define DRV_TIMER1_CONFIG \
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{TIM1, RCC_APB2Periph_TIM1, TIM1_UP_IRQn}
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#define DRV_TIMER2_CONFIG \
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{TIM2, RCC_APB1Periph_TIM2, TIM2_IRQn}
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#define DRV_TIMER3_CONFIG \
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{TIM3, RCC_APB1Periph_TIM3, TIM3_IRQn}
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#define DRV_TIMER4_CONFIG \
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{TIM4, RCC_APB1Periph_TIM4, TIM4_IRQn}
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#define DRV_TIMER5_CONFIG \
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{TIM5, RCC_APB1Periph_TIM5, TIM5_IRQn}
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#define DRV_TIMER1_INFO_CONFIG \
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{0, UINT16_MAX, UINT16_MAX}
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#define DRV_TIMER2_INFO_CONFIG \
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{0, UINT16_MAX, UINT16_MAX}
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#define DRV_TIMER3_INFO_CONFIG \
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{0, UINT16_MAX, UINT16_MAX}
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#define DRV_TIMER4_INFO_CONFIG \
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{0, UINT16_MAX, UINT16_MAX}
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#define DRV_TIMER5_INFO_CONFIG \
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{0, UINT16_MAX, UINT16_MAX}
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* _MR_BOARD_H_ */
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