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mr-library/device/i2c.c

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/*
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* @copyright (c) 2023-2024, MR Development Team
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*
* @license SPDX-License-Identifier: Apache-2.0
*
* @date 2023-11-09 MacRsh First version
*/
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#include "include/device/mr_i2c.h"
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#ifdef MR_USING_I2C
static int mr_i2c_bus_open(struct mr_dev *dev)
{
struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)dev;
struct mr_i2c_bus_ops *ops = (struct mr_i2c_bus_ops *)dev->drv->ops;
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/* Reset the hold */
i2c_bus->hold = MR_FALSE;
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/* Default address is 0x00 and 7-bit */
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return ops->configure(i2c_bus, &i2c_bus->config, 0x00, MR_I2C_ADDR_BITS_7);
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}
static int mr_i2c_bus_close(struct mr_dev *dev)
{
struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)dev;
struct mr_i2c_bus_ops *ops = (struct mr_i2c_bus_ops *)dev->drv->ops;
struct mr_i2c_config close_config = {0};
return ops->configure(i2c_bus, &close_config, 0x00, MR_I2C_ADDR_BITS_7);
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}
static ssize_t mr_i2c_bus_read(struct mr_dev *dev, void *buf, size_t count)
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{
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return MR_ENOTSUP;
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}
static ssize_t mr_i2c_bus_write(struct mr_dev *dev, const void *buf, size_t count)
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{
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return MR_ENOTSUP;
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}
static ssize_t mr_i2c_bus_isr(struct mr_dev *dev, int event, void *args)
{
struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)dev;
struct mr_i2c_bus_ops *ops = (struct mr_i2c_bus_ops *)i2c_bus->dev.drv->ops;
switch (event)
{
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case MR_ISR_I2C_RD_INT:
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{
struct mr_i2c_dev *i2c_dev = (struct mr_i2c_dev *)i2c_bus->owner;
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uint8_t data = ops->read(i2c_bus, MR_ENABLE);
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/* Read data to FIFO */
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mr_ringbuf_push_force(&i2c_dev->rd_fifo, data);
return (ssize_t)mr_ringbuf_get_data_size(&i2c_dev->rd_fifo);
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}
default:
{
return MR_ENOTSUP;
}
}
}
/**
* @brief This function registers a i2c-bus.
*
* @param i2c_bus The i2c-bus.
* @param path The path of the i2c-bus.
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* @param drv The driver of the i2c-bus.
*
* @return 0 on success, otherwise an error code.
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*/
int mr_i2c_bus_register(struct mr_i2c_bus *i2c_bus, const char *path, struct mr_drv *drv)
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{
static struct mr_dev_ops ops =
{
mr_i2c_bus_open,
mr_i2c_bus_close,
mr_i2c_bus_read,
mr_i2c_bus_write,
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MR_NULL,
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mr_i2c_bus_isr
};
struct mr_i2c_config default_config = MR_I2C_CONFIG_DEFAULT;
MR_ASSERT(i2c_bus != MR_NULL);
MR_ASSERT(path != MR_NULL);
MR_ASSERT(drv != MR_NULL);
MR_ASSERT(drv->ops != MR_NULL);
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/* Initialize the fields */
i2c_bus->config = default_config;
i2c_bus->owner = MR_NULL;
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i2c_bus->hold = MR_FALSE;
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/* Register the i2c-bus */
return mr_dev_register(&i2c_bus->dev, path, MR_DEV_TYPE_I2C, MR_O_RDWR, &ops, drv);
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}
MR_INLINE int i2c_dev_take_bus(struct mr_i2c_dev *i2c_dev)
{
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struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)i2c_dev->dev.parent;
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struct mr_i2c_bus_ops *ops = (struct mr_i2c_bus_ops *)i2c_bus->dev.drv->ops;
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/* Check if the bus is busy */
if ((i2c_bus->hold == MR_TRUE) && (i2c_dev != i2c_bus->owner))
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{
return MR_EBUSY;
}
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/* If the owner changes, recheck the configuration */
if (i2c_dev != i2c_bus->owner)
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{
if (i2c_dev->config.baud_rate != i2c_bus->config.baud_rate
|| i2c_dev->config.host_slave != i2c_bus->config.host_slave)
{
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int addr = (i2c_dev->config.host_slave == MR_I2C_SLAVE) ? i2c_dev->addr : 0x00;
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int ret = ops->configure(i2c_bus, &i2c_dev->config, addr, i2c_dev->addr_bits);
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if (ret < 0)
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{
return ret;
}
}
i2c_bus->config = i2c_dev->config;
i2c_bus->owner = i2c_dev;
}
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i2c_bus->hold = MR_TRUE;
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return MR_EOK;
}
MR_INLINE int i2c_dev_release_bus(struct mr_i2c_dev *i2c_dev)
{
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struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)i2c_dev->dev.parent;
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if (i2c_dev != i2c_bus->owner)
{
return MR_EINVAL;
}
/* If it is a host, release the bus. The slave needs to hold the bus at all times */
if (i2c_dev->config.host_slave == MR_I2C_HOST)
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{
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i2c_bus->hold = MR_FALSE;
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}
return MR_EOK;
}
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#define MR_I2C_RD (0)
#define MR_I2C_WR (1)
MR_INLINE void i2c_dev_send_addr(struct mr_i2c_dev *i2c_dev, int rdwr)
{
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struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)i2c_dev->dev.parent;
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struct mr_i2c_bus_ops *ops = (struct mr_i2c_bus_ops *)i2c_bus->dev.drv->ops;
int addr, addr_bits;
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/* Get the address, otherwise use the 0x00 */
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addr = i2c_dev->addr;
addr_bits = i2c_dev->addr_bits;
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/* Set the read command */
if (rdwr == MR_I2C_RD)
{
addr |= 0x01;
}
ops->start(i2c_bus);
ops->send_addr(i2c_bus, addr, addr_bits);
}
MR_INLINE void i2c_dev_send_stop(struct mr_i2c_dev *i2c_dev)
{
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struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)i2c_dev->dev.parent;
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struct mr_i2c_bus_ops *ops = (struct mr_i2c_bus_ops *)i2c_bus->dev.drv->ops;
ops->stop(i2c_bus);
}
MR_INLINE ssize_t i2c_dev_read(struct mr_i2c_dev *i2c_dev, uint8_t *buf, size_t count)
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{
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struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)i2c_dev->dev.parent;
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struct mr_i2c_bus_ops *ops = (struct mr_i2c_bus_ops *)i2c_bus->dev.drv->ops;
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uint8_t *rd_buf = (uint8_t *)buf;
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ssize_t rd_size;
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for (rd_size = 0; rd_size < count; rd_size += sizeof(*rd_buf))
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{
*rd_buf = ops->read(i2c_bus, (count - rd_size) == sizeof(*rd_buf));
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rd_buf++;
}
return rd_size;
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}
MR_INLINE ssize_t i2c_dev_write(struct mr_i2c_dev *i2c_dev, const uint8_t *buf, size_t count)
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{
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struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)i2c_dev->dev.parent;
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struct mr_i2c_bus_ops *ops = (struct mr_i2c_bus_ops *)i2c_bus->dev.drv->ops;
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uint8_t *wr_buf = (uint8_t *)buf;
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ssize_t wr_size;
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for (wr_size = 0; wr_size < count; wr_size += sizeof(*wr_buf))
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{
ops->write(i2c_bus, *wr_buf);
wr_buf++;
}
return wr_size;
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}
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static int mr_i2c_dev_open(struct mr_dev *dev)
{
struct mr_i2c_dev *i2c_dev = (struct mr_i2c_dev *)dev;
return mr_ringbuf_allocate(&i2c_dev->rd_fifo, i2c_dev->rd_bufsz);
}
static int mr_i2c_dev_close(struct mr_dev *dev)
{
struct mr_i2c_dev *i2c_dev = (struct mr_i2c_dev *)dev;
mr_ringbuf_free(&i2c_dev->rd_fifo);
return MR_EOK;
}
static ssize_t mr_i2c_dev_read(struct mr_dev *dev, void *buf, size_t count)
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{
struct mr_i2c_dev *i2c_dev = (struct mr_i2c_dev *)dev;
ssize_t ret = i2c_dev_take_bus(i2c_dev);
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if (ret < 0)
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{
return ret;
}
if (i2c_dev->config.host_slave == MR_I2C_HOST)
{
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/* Send the address of the register that needs to be read */
if (dev->position >= 0)
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{
i2c_dev_send_addr(i2c_dev, MR_I2C_WR);
i2c_dev_write(i2c_dev, (uint8_t *)&dev->position, (i2c_dev->config.reg_bits >> 3));
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}
i2c_dev_send_addr(i2c_dev, MR_I2C_RD);
ret = i2c_dev_read(i2c_dev, (uint8_t *)buf, count);
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i2c_dev_send_stop(i2c_dev);
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} else
{
if (mr_ringbuf_get_bufsz(&i2c_dev->rd_fifo) == 0)
{
ret = i2c_dev_read(i2c_dev, (uint8_t *)buf, count);
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} else
{
ret = (ssize_t)mr_ringbuf_read(&i2c_dev->rd_fifo, buf, count);
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}
}
i2c_dev_release_bus(i2c_dev);
return ret;
}
static ssize_t mr_i2c_dev_write(struct mr_dev *dev, const void *buf, size_t count)
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{
struct mr_i2c_dev *i2c_dev = (struct mr_i2c_dev *)dev;
ssize_t ret = i2c_dev_take_bus(i2c_dev);
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if (ret < 0)
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{
return ret;
}
if (i2c_dev->config.host_slave == MR_I2C_HOST)
{
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i2c_dev_send_addr(i2c_dev, MR_I2C_WR);
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/* Send the address of the register that needs to be written */
if (dev->position >= 0)
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{
i2c_dev_write(i2c_dev, (uint8_t *)&dev->position, (i2c_dev->config.reg_bits >> 3));
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}
ret = i2c_dev_write(i2c_dev, (uint8_t *)buf, count);
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i2c_dev_send_stop(i2c_dev);
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} else
{
ret = i2c_dev_write(i2c_dev, (uint8_t *)buf, count);
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}
i2c_dev_release_bus(i2c_dev);
return ret;
}
static int mr_i2c_dev_ioctl(struct mr_dev *dev, int cmd, void *args)
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{
struct mr_i2c_dev *i2c_dev = (struct mr_i2c_dev *)dev;
switch (cmd)
{
case MR_IOC_I2C_SET_CONFIG:
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{
if (args != MR_NULL)
{
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struct mr_i2c_bus *i2c_bus = (struct mr_i2c_bus *)dev->parent;
struct mr_i2c_config config = *(struct mr_i2c_config *)args;
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/* If holding the bus, release it */
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if (i2c_dev == i2c_bus->owner)
{
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i2c_bus->hold = MR_FALSE;
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i2c_bus->owner = MR_NULL;
}
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/* Update the configuration and try again to get the bus */
i2c_dev->config = config;
if (config.host_slave == MR_I2C_SLAVE)
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{
int ret = i2c_dev_take_bus(i2c_dev);
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if (ret < 0)
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{
return ret;
}
}
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return sizeof(config);
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}
return MR_EINVAL;
}
case MR_IOC_I2C_SET_RD_BUFSZ:
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{
if (args != MR_NULL)
{
size_t bufsz = *(size_t *)args;
int ret = mr_ringbuf_allocate(&i2c_dev->rd_fifo, bufsz);
i2c_dev->rd_bufsz = 0;
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if (ret < 0)
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{
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return ret;
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}
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i2c_dev->rd_bufsz = bufsz;
return sizeof(bufsz);
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}
return MR_EINVAL;
}
case MR_IOC_I2C_CLR_RD_BUF:
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{
mr_ringbuf_reset(&i2c_dev->rd_fifo);
return MR_EOK;
}
case MR_IOC_I2C_GET_CONFIG:
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{
if (args != MR_NULL)
{
struct mr_i2c_config *config = (struct mr_i2c_config *)args;
*config = i2c_dev->config;
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return sizeof(*config);
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}
return MR_EINVAL;
}
case MR_IOC_I2C_GET_RD_BUFSZ:
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{
if (args != MR_NULL)
{
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size_t *bufsz = (size_t *)args;
*bufsz = i2c_dev->rd_bufsz;
return sizeof(*bufsz);
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}
return MR_EINVAL;
}
case MR_IOC_I2C_GET_RD_DATASZ:
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{
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if (args != MR_NULL)
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{
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size_t *datasz = (size_t *)args;
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*datasz = mr_ringbuf_get_bufsz(&i2c_dev->rd_fifo);
return sizeof(*datasz);
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}
}
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default:
{
return MR_ENOTSUP;
}
}
}
/**
* @brief This function registers a i2c-device.
*
* @param i2c_dev The i2c-device.
* @param path The path of the i2c-device.
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* @param addr The address of the i2c-device.
* @param addr_bits The number of address bits of the i2c-device.
*
* @return 0 on success, otherwise an error code.
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*/
int mr_i2c_dev_register(struct mr_i2c_dev *i2c_dev, const char *path, int addr, int addr_bits)
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{
static struct mr_dev_ops ops =
{
mr_i2c_dev_open,
mr_i2c_dev_close,
mr_i2c_dev_read,
mr_i2c_dev_write,
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mr_i2c_dev_ioctl,
MR_NULL
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};
struct mr_i2c_config default_config = MR_I2C_CONFIG_DEFAULT;
MR_ASSERT(i2c_dev != MR_NULL);
MR_ASSERT(path != MR_NULL);
MR_ASSERT((addr_bits == MR_I2C_ADDR_BITS_7) || (addr_bits == MR_I2C_ADDR_BITS_10));
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/* Initialize the fields */
i2c_dev->config = default_config;
mr_ringbuf_init(&i2c_dev->rd_fifo, MR_NULL, 0);
#ifndef MR_CFG_I2C_RD_BUFSZ
#define MR_CFG_I2C_RD_BUFSZ (0)
#endif /* MR_CFG_I2C_RD_BUFSZ */
i2c_dev->rd_bufsz = MR_CFG_I2C_RD_BUFSZ;
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i2c_dev->addr = (addr_bits == MR_I2C_ADDR_BITS_7) ? addr : ((0xf0 | ((addr >> 7) & 0x06)) << 8) | (addr & 0xff);
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i2c_dev->addr_bits = addr_bits;
/* Register the i2c-device */
return mr_dev_register(&i2c_dev->dev, path, MR_DEV_TYPE_I2C, MR_O_RDWR, &ops, MR_NULL);
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}
#endif /* MR_USING_I2C */