119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
/**
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* @file arch.c
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* @author ATShining (1358745329@qq.com)
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* @brief
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* @version 0.1
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* @date 2023-09-25
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*
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* @copyright Copyright (c) 2023
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*
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*/
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#include "arch.h"
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#include "types.h"
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#include "util.h"
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#include "init.h"
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#include "config.h"
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#include "thread.h"
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#include "mk_sys.h"
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#include "mpu.h"
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#include "boot_info.h"
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#include "at32f435_437_clock.h"
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__ALIGN__(CONFIG_THREAD_BLOCK_SIZE)
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static uint8_t thread_knl_stack[CONFIG_THREAD_BLOCK_SIZE] = {0};
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void *_estack = thread_knl_stack + CONFIG_THREAD_BLOCK_SIZE;
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static boot_info_t boot_info; //!< 启动信息
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#define REG0_ADDR 0xE000ED22
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#define REG1_ADDR 0xE000ED04
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void arch_to_sche(void)
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{
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// 开启pensv中断
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; // 设置PendSV中断标志位
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_dmb();
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_dsb();
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_isb();
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}
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void sys_startup(void)
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{
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// 设置 systick 与 pendsv优先级为最低
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write_reg(REG0_ADDR, MASK_LSB(read_reg(REG0_ADDR), 16) | 0xffffUL);
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// 清空psp寄存器
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write_sysreg(0, psp);
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// 开启pensv中断
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write_reg(REG1_ADDR, 0x10000000);
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// 初始化systick时钟
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SysTick_Config(SystemCoreClock / CONFIG_SYS_SCHE_HZ);
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}
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void sys_reset(void)
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{
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__set_FAULTMASK(1); // 关闭所有中端
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NVIC_SystemReset(); // 复位
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}
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void arch_disable_irq(int inx)
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{
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NVIC_DisableIRQ(inx);
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}
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void arch_enable_irq(int inx)
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{
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NVIC_EnableIRQ(inx);
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}
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uint32_t arch_get_sys_clk(void)
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{
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extern uint32_t SystemCoreClock;
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return SystemCoreClock;
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}
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void arch_set_enable_irq_prio(int inx, int sub_prio, int pre_prio)
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{
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nvic_irq_enable(inx, sub_prio, pre_prio);
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}
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void arch_set_boot_info(void *bi)
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{
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boot_info = *((boot_info_t *)bi);
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printk("==============================sys flash layer info============================\n");
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for (int i = 0; i < boot_info.flash_layer.flash_layer_num; i++)
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{
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printk("[%d]\t[0x%x 0x%x]\t%s %dB\n", i,
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boot_info.flash_layer.flash_layer_list[i].st_addr,
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boot_info.flash_layer.flash_layer_list[i].st_addr + boot_info.flash_layer.flash_layer_list[i].size - 1,
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boot_info.flash_layer.flash_layer_list[i].name,
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boot_info.flash_layer.flash_layer_list[i].size);
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}
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printk("=======================================================================\n");
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printk("==============================sys flash info============================\n");
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for (int i = 0; i < boot_info.flash.flash_num; i++)
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{
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printk("[%d]\t[0x%x 0x%x] %dB\n", i,
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boot_info.flash.flash_list[i].addr,
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boot_info.flash.flash_list[i].addr + boot_info.flash.flash_list[i].size - 1,
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boot_info.flash.flash_list[i].size);
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}
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printk("=======================================================================\n");
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printk("==============================sys mem info============================\n");
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for (int i = 0; i < boot_info.mem.mem_num; i++)
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{
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printk("[%d]\t[0x%x 0x%x] %dB\n", i,
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boot_info.mem.mem_list[i].addr,
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boot_info.mem.mem_list[i].addr + boot_info.mem.mem_list[i].size - 1,
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boot_info.mem.mem_list[i].size);
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}
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printk("=======================================================================\n");
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}
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boot_info_t *arch_get_boot_info(void)
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{
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return &boot_info;
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}
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void arch_init(void)
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{
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SystemInit();
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system_clock_config();
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mpu_init();
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SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;
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SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
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((uint8_t *)(0xE000E008))[0] |= 0x6;
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// RCC_ClocksTypeDef RCC_ClocksStatus;
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// RCC_GetClocksFreq(&RCC_ClocksStatus);
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}
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INIT_LOW_HARD(arch_init);
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