201 lines
6.3 KiB
C
Executable File
201 lines
6.3 KiB
C
Executable File
#ifndef _SYSREGS_H
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#define _SYSREGS_H
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#include "types_asm.h"
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/*
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* SCTLR_EL1, System Control Register (EL1)
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* AArch64-Reference-Manual v8.6, D13.2.113
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*/
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/* Common SCTLR_ELx flags. */
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#define SCTLR_ELx_DSSBS (_BITUL(44))
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#define SCTLR_ELx_ENIA (_BITUL(31))
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#define SCTLR_ELx_ENIB (_BITUL(30))
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#define SCTLR_ELx_ENDA (_BITUL(27))
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#define SCTLR_ELx_EE (_BITUL(25))
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#define SCTLR_ELx_IESB (_BITUL(21))
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#define SCTLR_ELx_WXN (_BITUL(19))
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#define SCTLR_ELx_ENDB (_BITUL(13))
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#define SCTLR_ELx_I (_BITUL(12))
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#define SCTLR_ELx_SA (_BITUL(3))
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#define SCTLR_ELx_C (_BITUL(2))
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#define SCTLR_ELx_A (_BITUL(1))
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#define SCTLR_ELx_M (_BITUL(0))
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#define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
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SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
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/* SCTLR_EL2 specific flags. */
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#define SCTLR_EL2_RES1 \
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((_BITUL(4)) | (_BITUL(5)) | (_BITUL(11)) | (_BITUL(16)) | \
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(_BITUL(18)) | (_BITUL(22)) | (_BITUL(23)) | (_BITUL(28)) | \
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(_BITUL(29)))
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#define SCTLR_EL2_RES0 \
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((_BITUL(6)) | (_BITUL(7)) | (_BITUL(8)) | (_BITUL(9)) | \
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(_BITUL(10)) | (_BITUL(13)) | (_BITUL(14)) | (_BITUL(15)) | \
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(_BITUL(17)) | (_BITUL(20)) | (_BITUL(24)) | (_BITUL(26)) | \
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(_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \
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(0xffffefffUL << 32))
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define ENDIAN_SET_EL2 SCTLR_ELx_EE
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#define ENDIAN_CLEAR_EL2 0
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#else
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#define ENDIAN_SET_EL2 0
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#define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE
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#endif
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/* SCTLR_EL2 value used for the hyp-stub */
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#define SCTLR_EL2_SET (SCTLR_ELx_IESB | ENDIAN_SET_EL2 | SCTLR_EL2_RES1)
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#define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
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SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \
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SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
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#define SCTLR_EL2_VALUE_MMU_DISABLED (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
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/* SCTLR_EL1 specific flags. */
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#define SCTLR_EL1_UCI (_BITUL(26))
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#define SCTLR_EL1_E0E (_BITUL(24))
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#define SCTLR_EL1_SPAN (_BITUL(23))
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#define SCTLR_EL1_NTWE (_BITUL(18))
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#define SCTLR_EL1_NTWI (_BITUL(16))
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#define SCTLR_EL1_UCT (_BITUL(15))
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#define SCTLR_EL1_DZE (_BITUL(14))
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#define SCTLR_EL1_UMA (_BITUL(9))
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#define SCTLR_EL1_SED (_BITUL(8))
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#define SCTLR_EL1_ITD (_BITUL(7))
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#define SCTLR_EL1_CP15BEN (_BITUL(5))
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#define SCTLR_EL1_SA0 (_BITUL(4))
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#define SCTLR_EL1_RES1 \
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((_BITUL(11)) | (_BITUL(20)) | (_BITUL(22)) | (_BITUL(28)) | \
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(_BITUL(29)))
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#define SCTLR_EL1_RES0 \
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((_BITUL(6)) | (_BITUL(10)) | (_BITUL(13)) | (_BITUL(17)) | \
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(_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \
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(0xffffefffUL << 32))
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
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#define ENDIAN_CLEAR_EL1 0
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#else
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#define ENDIAN_SET_EL1 0
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#define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
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#endif
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#define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\
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SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\
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SCTLR_EL1_DZE | SCTLR_EL1_UCT |\
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SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
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ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1)
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#define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\
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SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\
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SCTLR_ELx_DSSBS | SCTLR_EL1_NTWI | SCTLR_EL1_RES0)
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#define SCTLR_EL1_VALUE_MMU_DISABLED (SCTLR_EL1_RES1 | ENDIAN_SET_EL1)
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/*
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* HCR_EL2, Hypervisor Configuration Register (EL2)
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* AArch64-Reference-Manual v8.6, D13.2.47
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*/
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#define HCR_FWB (UL(1) << 46)
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#define HCR_API (UL(1) << 41)
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#define HCR_APK (UL(1) << 40)
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#define HCR_TEA (UL(1) << 37)
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#define HCR_TERR (UL(1) << 36)
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#define HCR_TLOR (UL(1) << 35)
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#define HCR_E2H (UL(1) << 34)
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#define HCR_ID (UL(1) << 33)
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#define HCR_CD (UL(1) << 32)
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#define HCR_RW_SHIFT 31
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#define HCR_RW (UL(1) << HCR_RW_SHIFT)
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#define HCR_TRVM (UL(1) << 30)
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#define HCR_HCD (UL(1) << 29)
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#define HCR_TDZ (UL(1) << 28)
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#define HCR_TGE (UL(1) << 27)
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#define HCR_TVM (UL(1) << 26)
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#define HCR_TTLB (UL(1) << 25)
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#define HCR_TPU (UL(1) << 24)
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#define HCR_TPC (UL(1) << 23)
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#define HCR_TSW (UL(1) << 22)
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#define HCR_TAC (UL(1) << 21)
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#define HCR_TIDCP (UL(1) << 20)
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#define HCR_TSC (UL(1) << 19)
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#define HCR_TID3 (UL(1) << 18)
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#define HCR_TID2 (UL(1) << 17)
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#define HCR_TID1 (UL(1) << 16)
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#define HCR_TID0 (UL(1) << 15)
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#define HCR_TWE (UL(1) << 14)
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#define HCR_TWI (UL(1) << 13)
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#define HCR_DC (UL(1) << 12)
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#define HCR_BSU (3 << 10)
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#define HCR_BSU_IS (UL(1) << 10)
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#define HCR_FB (UL(1) << 9)
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#define HCR_VSE (UL(1) << 8)
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#define HCR_VI (UL(1) << 7)
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#define HCR_VF (UL(1) << 6)
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#define HCR_AMO (UL(1) << 5)
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#define HCR_IMO (UL(1) << 4)
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#define HCR_FMO (UL(1) << 3)
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#define HCR_PTW (UL(1) << 2)
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#define HCR_SWIO (UL(1) << 1)
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#define HCR_VM (UL(1) << 0)
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/*
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* The bits we set in HCR:
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* TLOR: Trap LORegion register accesses
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* RW: 64bit by default, can be overridden for 32bit VMs
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* TAC: Trap ACTLR
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* TSC: Trap SMC
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* TVM: Trap VM ops (until M+C set in SCTLR_EL1)
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* TSW: Trap cache operations by set/way
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* TWE: Trap WFE
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* TWI: Trap WFI
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* TIDCP: Trap L2CTLR/L2ECTLR
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* BSU_IS: Upgrade barriers to the inner shareable domain
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* FB: Force broadcast of all maintenance operations
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* AMO: Override CPSR.A and enable signaling with VA
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* IMO: Override CPSR.I and enable signaling with VI
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* FMO: Override CPSR.F and enable signaling with VF
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* SWIO: Turn set/way invalidates into set/way clean+invalidate
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*/
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#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
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HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
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HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
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HCR_FMO | HCR_IMO)
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#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
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#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_E2H)
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#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
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/*
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* SCR_EL3, Secure Configuration Register (EL3), Page 2648 of
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* AArch64-Reference-Manual.
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*/
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#define SCR_RESERVED (3 << 4)
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#define SCR_RW (1 << 10)
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#define SCR_NS (1 << 0)
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// #define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_NS)
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#define SCR_VALUE (\
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SCR_NS|SCR_RW|(1UL<<7)|(1UL<<8)\
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)
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/*
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* SPSR_EL3, Saved Program Status Register (EL3) Page 389 of
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* AArch64-Reference-Manual.
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*/
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#define SPSR_MASK_ALL (7 << 6)
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#define SPSR_EL1h (5 << 0)
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#define SPSR_EL2h (9 << 0)
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#define SPSR_EL1 (SPSR_MASK_ALL | SPSR_EL1h)
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#define SPSR_EL2 (SPSR_MASK_ALL | SPSR_EL2h)
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/* Current Exception Level values, as contained in CurrentEL */
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#define CurrentEL_EL1 (1 << 2)
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#define CurrentEL_EL2 (2 << 2)
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#define CurrentEL_EL3 (3 << 2)
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#endif
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