291 lines
9.0 KiB
C
291 lines
9.0 KiB
C
#pragma once
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#include <types.h>
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#include <arch.h>
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#include <printk.h>
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#include <util.h>
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#include <assert.h>
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// #include <timer.h>
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/*
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* ID0-ID15，分配给SGI (一般会将0-7给REE,8-15给TEE)
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* ID16-ID31，分配给PPI
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* ID32-ID1019，分配给SPI
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* ID1020-ID1023，特殊中断号
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* ID1024-ID8191，reserved
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* 8192及其以上，LPI
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*/
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typedef struct gic
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{
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uint16_t irqs_number; //!< 支持的irq数量
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addr_t disp_base_addr; //!< 分发器起始地址
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addr_t inter_base_addr; //!< 接口起始地址
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} gic_t;
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// #define GIC2_BASE (0xFF840000)
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// #define GIC2_GICD_BASE (GIC2_BASE + 0x1000)
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#define GICD_CTLR(GIC2_GICD_BASE) (0x0 + GIC2_GICD_BASE)
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#define GICD_TYPER(GIC2_GICD_BASE) (0x4 + GIC2_GICD_BASE)
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#define GICD_IIDR(GIC2_GICD_BASE) (0x8 + GIC2_GICD_BASE)
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#define GICD_IGROUPRn(GIC2_GICD_BASE) (0x80 + GIC2_GICD_BASE)
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#define GICD_ISENABLERn(GIC2_GICD_BASE) (0x100 + GIC2_GICD_BASE)
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#define GICD_ICENABLERn(GIC2_GICD_BASE) (0x180 + GIC2_GICD_BASE)
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#define GICD_ISPENDRn(GIC2_GICD_BASE) (0x200 + GIC2_GICD_BASE)
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#define GICD_ICPENDRn(GIC2_GICD_BASE) (0x280 + GIC2_GICD_BASE)
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#define GICD_ISACTIVERn(GIC2_GICD_BASE) (0x300 + GIC2_GICD_BASE)
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#define GICD_ICACTIVERn(GIC2_GICD_BASE) (0x380 + GIC2_GICD_BASE)
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#define GICD_IPRIORITYRn(GIC2_GICD_BASE) (0x400 + GIC2_GICD_BASE)
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#define GICD_ITARGETSRn(GIC2_GICD_BASE) (0x800 + GIC2_GICD_BASE)
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#define GICD_ICFGRn(GIC2_GICD_BASE) (0xC00 + GIC2_GICD_BASE)
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#define GICD_SGIR(GIC2_GICD_BASE) (0xf00 + GIC2_GICD_BASE)
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#define GICD_CPENDSGIRn(GIC2_GICD_BASE) (0xf10 + GIC2_GICD_BASE)
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#define GICD_SPENDSGIRn(GIC2_GICD_BASE) (0xf20 + GIC2_GICD_BASE)
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// #define (GIC2_GICC_BASE) (GIC2_BASE + 0x2000)
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#define GICC_CTLR(GIC2_GICC_BASE) (0x0 + GIC2_GICC_BASE)
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#define GICC_PMR(GIC2_GICC_BASE) (0x4 + GIC2_GICC_BASE)
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#define GICC_BPR(GIC2_GICC_BASE) (0x8 + GIC2_GICC_BASE)
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#define GICC_IAR(GIC2_GICC_BASE) (0xc + GIC2_GICC_BASE)
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#define GICC_EOIR(GIC2_GICC_BASE) (0x10 + GIC2_GICC_BASE)
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#define GICC_RPR(GIC2_GICC_BASE) (0x14 + GIC2_GICC_BASE)
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#define GICC_HPPIR(GIC2_GICC_BASE) (0x18 + GIC2_GICC_BASE)
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#define GICC_APRn(GIC2_GICC_BASE) (0xd0 + GIC2_GICC_BASE)
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#define GICC_IIDR(GIC2_GICC_BASE) (0x00FC + GIC2_GICC_BASE)
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#define MAX_INTR_NO 1020
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static inline void gic2_set_disp_cpu(gic_t *irq, uint64_t cpu_mask)
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{
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write_reg32(GICD_SGIR(irq->disp_base_addr),
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read_reg32(GICD_SGIR(irq->disp_base_addr)) |
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((cpu_mask & 0xff) << 16UL));
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}
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static inline void gic2_clear_disp_cpu(gic_t *irq, uint8_t cpu_mask)
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{
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write_reg32(GICD_SGIR(irq->disp_base_addr),
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read_reg32(GICD_SGIR(irq->disp_base_addr)) &
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((~(cpu_mask & 0xff)) << 16UL));
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}
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static inline void gic2_set_unmask(gic_t *irq, uint64_t inx)
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{
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assert(inx < MAX_INTR_NO);
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void *addr = (void *)(GICD_ISENABLERn(irq->disp_base_addr) + ((inx >> 5) << 2));
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uint32_t tmp = read_reg32(addr);
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uint32_t bit_inx = inx % 32;
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MK_CLR_BIT(tmp, bit_inx);
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tmp |= (1) << bit_inx;
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write_reg32((uint32_t *)addr, tmp);
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}
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static inline void gic2_set_mask(gic_t *irq, uint64_t inx)
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{
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assert(inx < MAX_INTR_NO);
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void *addr = (void *)(GICD_ICENABLERn(irq->disp_base_addr) + ((inx >> 5) << 2));
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uint32_t tmp = read_reg32(addr);
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uint32_t bit_inx = inx % 32;
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MK_CLR_BIT(tmp, bit_inx);
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tmp |= (1) << bit_inx;
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write_reg32((uint32_t *)addr, tmp);
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}
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static inline bool_t gic2_get_mask(gic_t *irq, uint64_t inx)
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{
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assert(inx < MAX_INTR_NO);
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void *addr = (void *)(GICD_ISENABLERn(irq->disp_base_addr) +
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((inx >> 5) << 2));
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uint32_t tmp = read_reg32((uint32_t *)addr);
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uint32_t bit_inx = inx % 32;
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return !!((tmp >> bit_inx) & 0x1ul);
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}
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static inline void gic2_set_active(gic_t *irq, uint64_t inx)
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{
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assert(inx < MAX_INTR_NO);
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void *addr = (void *)(GICD_ISACTIVERn(irq->disp_base_addr) + ((inx >> 5) << 2));
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uint32_t tmp = read_reg32(addr);
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uint32_t bit_inx = inx % 32;
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MK_CLR_BIT(tmp, bit_inx);
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tmp |= (1) << bit_inx;
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write_reg32((uint32_t *)addr, tmp);
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}
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static inline void gic2_clear_active(gic_t *irq, uint64_t inx)
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{
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assert(inx < MAX_INTR_NO);
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void *addr = (void *)(GICD_ICACTIVERn(irq->disp_base_addr) + ((inx >> 5) << 2));
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uint32_t tmp = read_reg32(addr);
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uint32_t bit_inx = inx % 32;
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MK_CLR_BIT(tmp, bit_inx);
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tmp |= (1) << bit_inx;
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write_reg32((uint32_t *)addr, tmp);
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}
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static inline void gic2_set_pending(gic_t *irq, uint64_t inx)
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{
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assert(inx < MAX_INTR_NO);
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void *addr = (void *)(GICD_ISPENDRn(irq->disp_base_addr) + ((inx >> 5) << 2));
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uint32_t tmp = read_reg32(addr);
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uint32_t bit_inx = inx % 32;
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MK_CLR_BIT(tmp, bit_inx);
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tmp |= (1) << bit_inx;
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write_reg32((uint32_t *)addr, tmp);
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}
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static inline void gic2_clear_pending(gic_t *irq, uint64_t inx)
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{
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assert(inx < MAX_INTR_NO);
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void *addr = (void *)(GICD_ICPENDRn(irq->disp_base_addr) + ((inx >> 5) << 2));
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uint32_t tmp = read_reg32(addr);
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uint32_t bit_inx = inx % 32;
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MK_CLR_BIT(tmp, bit_inx);
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tmp |= (1) << bit_inx;
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write_reg32((uint32_t *)addr, tmp);
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}
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static inline void gic2_set_target_cpu(gic_t *irq, uint64_t inx, uint64_t target_cpu)
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{
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assert(inx < MAX_INTR_NO);
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// assert(target_cpu < 8);
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void *addr = (void *)(GICD_ITARGETSRn((irq->disp_base_addr)) +
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((inx >> 2) << 2));
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uint32_t bit_inx = inx % 4;
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uint32_t tmp = read_reg32((uint32_t *)addr);
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tmp &= ~(0xffUL << (bit_inx << 3));
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tmp |= target_cpu << (bit_inx << 3);
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write_reg32((uint32_t *)addr, tmp);
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tmp = read_reg32((uint32_t *)addr);
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}
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static inline uint64_t gic2_get_target_cpu(gic_t *irq, uint64_t inx)
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{
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assert(inx < MAX_INTR_NO);
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void *addr = (void *)(GICD_ITARGETSRn(irq->disp_base_addr) +
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((inx >> 2) << 2));
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uint32_t bit_inx = inx % 4;
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uint32_t tmp = read_reg32((uint32_t *)addr);
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return (tmp >> (bit_inx << 3)) & 0xff;
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}
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static inline void gic2_set_edge_mode(gic_t *irq, int inx, int mode)
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{
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uint32_t tmp = read_reg32(GICD_ICFGRn(irq->disp_base_addr) +
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((inx >> 4) << 2));
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tmp &= ~(0x3ul << ((inx % 16) << 1));
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tmp |= (!!mode << 1) << ((inx % 16) << 1);
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write_reg32(GICD_ICFGRn(irq->disp_base_addr) +
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((inx >> 4) << 2),
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tmp);
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}
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static inline int gic2_get_edge_mode(gic_t *irq, int inx)
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{
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uint32_t tmp = read_reg32(GICD_ICFGRn(irq->disp_base_addr) +
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((inx >> 4) << 2));
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return ((tmp >> ((inx % 16) << 1)) & 0x3UL) >> 1;
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}
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static inline void gic_enable(gic_t *irq)
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{
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write_reg32(GICD_CTLR(irq->disp_base_addr), TRUE);
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}
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static inline void gic_disable(gic_t *irq)
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{
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write_reg32(GICD_CTLR(irq->disp_base_addr), FALSE);
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}
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static inline void gic2_set_prio(gic_t *irq, int inx, uint64_t prio)
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{
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uint32_t tmp = read_reg32(GICD_IPRIORITYRn(irq->disp_base_addr) +
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((inx >> 2) << 2));
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tmp &= ~(0xffUL << ((inx % 4) << 3));
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tmp |= (prio & 0xffUL) << ((inx % 4) << 3);
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write_reg32(GICD_IPRIORITYRn(irq->disp_base_addr) +
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((inx >> 2) << 2),
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tmp);
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}
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static inline uint8_t gic2_get_prio(gic_t *irq, int inx)
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{
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uint32_t tmp = read_reg32(GICD_IPRIORITYRn(irq->disp_base_addr) +
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((inx >> 2) << 2));
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return ((tmp) >> ((inx % 4) << 3)) & 0xffUL;
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}
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// cpu inter
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static inline void gic2_cpu_enable(gic_t *irq)
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{
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write_reg32(GICC_CTLR(irq->inter_base_addr), TRUE);
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}
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static inline void gic2_cpu_disable(gic_t *irq)
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{
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write_reg32(GICC_CTLR(irq->inter_base_addr), FALSE);
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}
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static inline void gic_dist_init(gic_t *irq)
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{
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gic_disable(irq);
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for (int i = 32; i < irq->irqs_number; i++)
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{
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gic2_set_unmask(irq, i);
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gic2_set_edge_mode(irq, i, 0);
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gic2_clear_active(irq, i);
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}
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for (int i = 0; i < 16; i++)
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{
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gic2_set_unmask(irq, i);
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}
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gic_enable(irq);
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}
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static inline void gic_inter_init(gic_t *irq)
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{
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for (int i = 0; i < 32; i++)
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{
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gic2_set_prio(irq, i, 0xa0);
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}
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write_reg32(GICC_PMR(irq->inter_base_addr), 0xf0UL);
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gic2_cpu_enable(irq);
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}
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static inline void gic2_eoi_irq(gic_t *irq, int inx)
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{
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write_reg32(GICC_EOIR(irq->inter_base_addr), inx);
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}
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static inline void gic_init(gic_t *irq, addr_t disp_addr, addr_t inter_addr)
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{
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irq->irqs_number = ((read_reg32(GICD_TYPER(disp_addr)) & 0x1ful) + 1) * 32;
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if (irq->irqs_number > MAX_INTR_NO)
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{
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irq->irqs_number = MAX_INTR_NO;
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}
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irq->disp_base_addr = disp_addr;
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irq->inter_base_addr = inter_addr;
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printk("irqs_number %d, disp_base 0x%lx inter_base 0x%lx.\n", irq->irqs_number, irq->disp_base_addr, irq->inter_base_addr);
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gic_dist_init(irq);
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gic_inter_init(irq);
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}
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gic_t *arm_gicv2_get_global(void);
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// static inline void gic_handle_irq(void)
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// {
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// extern gic_t m_irq;
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// do
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// {
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// uint32_t irqstat =
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// read_reg32(GICC_IAR(m_irq.inter_base_addr));
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// uint32_t irqnr = irqstat & 0x3ff;
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// if (irqnr == 30)
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// handle_timer_irq();
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// gic2_eoi_irq(&m_irq, irqnr);
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// } while (0);
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// }
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