195 lines
6.6 KiB
C
195 lines
6.6 KiB
C
#pragma once
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/* GPR related macros & defines */
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#define CPU_GPR_COUNT 30
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/* ESR_EL2 */
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#define ESR_INITVAL 0x00000000LU
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#define ESR_EC_MASK 0xFC000000LU
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#define ESR_EC_SHIFT 26
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#define ESR_IL_MASK 0x02000000LU
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#define ESR_IL_SHIFT 25
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#define ESR_ISS_MASK 0x01FFFFFFLU
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#define ESR_ISS_SHIFT 0
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/* Exception Class (EC) Values */
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#define EC_UNKNOWN 0x00
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#define EC_TRAP_WFI_WFE 0x01
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#define EC_TRAP_MCR_MRC_CP15_A32 0x03
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#define EC_TRAP_MCRR_MRRC_CP15_A32 0x04
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#define EC_TRAP_MCR_MRC_CP14_A32 0x05
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#define EC_TRAP_LDC_STC_CP14_A32 0x06
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#define EC_SIMD_FPU 0x07
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#define EC_TRAP_MRC_VMRS_CP10_A32 0x08
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#define EC_TRAP_MCRR_MRRC_CP14_A32 0x0C
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#define EC_TRAP_IL 0x0E
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#define EC_TRAP_SVC_A32 0x11
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#define EC_TRAP_HVC_A32 0x12
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#define EC_TRAP_SMC_A32 0x13
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#define EC_TRAP_SVC_A64 0x15
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#define EC_TRAP_HVC_A64 0x16
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#define EC_TRAP_SMC_A64 0x17
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#define EC_TRAP_MSR_MRS_SYSTEM 0x18
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#define EC_TRAP_LWREL_INST_ABORT 0x20
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#define EC_CUREL_INST_ABORT 0x21
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#define EC_PC_UNALIGNED 0x22
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#define EC_TRAP_LWREL_DATA_ABORT 0x24
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#define EC_CUREL_DATA_ABORT 0x25
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#define EC_SP_UNALIGNED 0x26
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#define EC_FPEXC_A32 0x28
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#define EC_FPEXC_A64 0x2C
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#define EC_SERROR 0x2F
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#define EC_DBG_EXC_MASK 0x30
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/* Instruction/Data Abort ISS Encodings */
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#define ISS_ABORT_ISV_MASK 0x01000000
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#define ISS_ABORT_ISV_SHIFT 24
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#define ISS_ABORT_SAS_MASK 0x00C00000
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#define ISS_ABORT_SAS_SHIFT 22
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#define ISS_ABORT_SSE_MASK 0x00200000
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#define ISS_ABORT_SSE_SHIFT 21
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#define ISS_ABORT_SRT_MASK 0x001F0000
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#define ISS_ABORT_SRT_SHIFT 16
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#define ISS_ABORT_SF_MASK 0x00008000
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#define ISS_ABORT_SF_SHIFT 15
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#define ISS_ABORT_AR_MASK 0x00004000
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#define ISS_ABORT_AR_SHIFT 14
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#define ISS_ABORT_EA_MASK 0x00000200
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#define ISS_ABORT_EA_SHIFT 9
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#define ISS_ABORT_CM_MASK 0x00000100
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#define ISS_ABORT_CM_SHIFT 8
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#define ISS_ABORT_S1PTW_MASK 0x00000080
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#define ISS_ABORT_S1PTW_SHIFT 7
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#define ISS_ABORT_WNR_MASK 0x00000040
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#define ISS_ABORT_WNR_SHIFT 6
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#define ISS_ABORT_FSC_MASK 0x0000003F
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#define ISS_ABORT_FSC_SHIFT 0
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/* Fault Status (IFSC/DFSC) Encodings */
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#define FSC_TRANS_FAULT_LEVEL0 0x04
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#define FSC_TRANS_FAULT_LEVEL1 0x05
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#define FSC_TRANS_FAULT_LEVEL2 0x06
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#define FSC_TRANS_FAULT_LEVEL3 0x07
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#define FSC_ACCESS_FAULT_LEVEL0 0x08
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#define FSC_ACCESS_FAULT_LEVEL1 0x09
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#define FSC_ACCESS_FAULT_LEVEL2 0x0A
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#define FSC_ACCESS_FAULT_LEVEL3 0x0B
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#define FSC_PERM_FAULT_LEVEL0 0x0C
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#define FSC_PERM_FAULT_LEVEL1 0x0D
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#define FSC_PERM_FAULT_LEVEL2 0x0E
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#define FSC_PERM_FAULT_LEVEL3 0x0F
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#define FSC_SYNC_EXTERNAL_ABORT 0x10
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#define FSC_ASYNC_EXTERNAL_ABORT 0x11
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#define FSC_SYNC_TWALK_EXTERNAL_ABORT_LEVEL0 0x14
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#define FSC_SYNC_TWALK_EXTERNAL_ABORT_LEVEL1 0x15
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#define FSC_SYNC_TWALK_EXTERNAL_ABORT_LEVEL2 0x16
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#define FSC_SYNC_TWALK_EXTERNAL_ABORT_LEVEL3 0x17
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#define FSC_SYNC_PARITY_ERROR 0x18
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#define FSC_ASYNC_PARITY_ERROR 0x19
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#define FSC_SYNC_TWALK_PARITY_ERROR_LEVEL0 0x1C
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#define FSC_SYNC_TWALK_PARITY_ERROR_LEVEL1 0x1D
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#define FSC_SYNC_TWALK_PARITY_ERROR_LEVEL2 0x1E
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#define FSC_SYNC_TWALK_PARITY_ERROR_LEVEL3 0x1F
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#define FSC_ALIGN_FAULT 0x21
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#define FSC_DEBUG_EVENT 0x22
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#define FSC_TLB_CONFLICT_ABORT 0x30
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#define FSC_DOMAIN_FAULT_LEVEL0 0x3C
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#define FSC_DOMAIN_FAULT_LEVEL1 0x3D
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#define FSC_DOMAIN_FAULT_LEVEL2 0x3E
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#define FSC_DOMAIN_FAULT_LEVEL3 0x3F
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#define PSR_MODE32 0x00000010
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#define PSR_MODE32_MASK 0x0000001f
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#define PSR_MODE32_USER 0x00000010
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#define PSR_MODE32_FIQ 0x00000011
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#define PSR_MODE32_IRQ 0x00000012
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#define PSR_MODE32_SUPERVISOR 0x00000013
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#define PSR_MODE32_MONITOR 0x00000016
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#define PSR_MODE32_ABORT 0x00000017
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#define PSR_MODE32_HYPERVISOR 0x0000001a
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#define PSR_MODE32_UNDEFINED 0x0000001b
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#define PSR_MODE32_SYSTEM 0x0000001f
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#define PSR_FIQ_DISABLED (1 << 6)
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#define PSR_IRQ_DISABLED (1 << 7)
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#define PSR_ASYNC_ABORT_DISABLED (1 << 8)
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#define PSR_MODE64_DEBUG_DISABLED (1 << 9)
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#define PSR_MODE32_BE_ENABLED (1 << 9)
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#define PSR_IL_MASK 0x00100000
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#define PSR_IL_SHIFT 20
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#define PSR_SS_MASK 0x00200000
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#define PSR_SS_SHIFT 21
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#define PSR_OVERFLOW_MASK (1 << 28)
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#define PSR_OVERFLOW_SHIFT 28
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#define PSR_CARRY_MASK (1 << 29)
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#define PSR_CARRY_SHIFT 29
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#define PSR_ZERO_MASK (1 << 30)
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#define PSR_ZERO_SHIFT 30
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#define PSR_NEGATIVE_MASK (1 << 31)
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#define PSR_NEGATIVE_SHIFT 31
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/* Fields of AArch32-PSR which will be RES0 in Aarch64 */
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/* Section 3.8.8 Unused fields of SPSR - Exception Model */
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#define PSR_THUMB_ENABLED (1 << 5)
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#define PSR_IT2_MASK 0x0000FC00
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#define PSR_IT2_SHIFT 10
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#define PSR_GE_MASK 0x000F0000
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#define PSR_GE_SHIFT 16
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#define PSR_JAZZLE_ENABLED (1 << 24)
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#define PSR_IT1_MASK 0x06000000
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#define PSR_IT1_SHIFT 25
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#define PSR_CUMMULATE_MASK (1 << 27)
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#define PSR_CUMMULATE_SHIFT 27
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#define PSR_NZCV_MASK (PSR_NEGATIVE_MASK | \
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PSR_ZERO_MASK | \
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PSR_CARRY_MASK | \
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PSR_OVERFLOW_MASK)
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#define PSR_IT_MASK (PSR_IT2_MASK | \
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PSR_IT1_MASK)
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#define PSR_USERBITS_MASK (PSR_NZCV_MASK | \
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PSR_CUMMULATE_MASK | \
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PSR_GE_MASK | \
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PSR_IT_MASK | \
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PSR_THUMB_ENABLED)
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#define PSR_PRIVBITS_MASK (~PSR_USERBITS_MASK)
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#define PSR_ALLBITS_MASK 0xFFFFFFFF
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#define CPSR_MODE_MASK PSR_MODE32_MASK
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#define CPSR_MODE_USER PSR_MODE32_USER
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#define CPSR_MODE_FIQ PSR_MODE32_FIQ
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#define CPSR_MODE_IRQ PSR_MODE32_IRQ
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#define CPSR_MODE_SUPERVISOR PSR_MODE32_SUPERVISOR
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#define CPSR_MODE_MONITOR PSR_MODE32_MONITOR
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#define CPSR_MODE_ABORT PSR_MODE32_ABORT
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#define CPSR_MODE_HYPERVISOR PSR_MODE32_HYPERVISOR
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#define CPSR_MODE_UNDEFINED PSR_MODE32_UNDEFINED
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#define CPSR_MODE_SYSTEM PSR_MODE32_SYSTEM
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#define CPSR_THUMB_ENABLED PSR_THUMB_ENABLED
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#define CPSR_FIQ_DISABLED PSR_FIQ_DISABLED
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#define CPSR_IRQ_DISABLED PSR_IRQ_DISABLED
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#define CPSR_ASYNC_ABORT_DISABLED PSR_ASYNC_ABORT_DISABLED
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#define CPSR_BE_ENABLED PSR_MODE32_BE_ENABLED
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#define CPSR_IT2_MASK PSR_IT2_MASK
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#define CPSR_IT2_SHIFT PSR_IT2_SHIFT
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#define CPSR_GE_MASK PSR_GE_MASK
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#define CPSR_GE_SHIFT PSR_GE_SHIFT
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#define CPSR_JAZZLE_ENABLED PSR_JAZZLE_ENABLED
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#define CPSR_IT1_MASK PSR_IT1_MASK
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#define CPSR_IT1_SHIFT PSR_IT1_SHIFT
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#define CPSR_CUMMULATE_MASK PSR_CUMMULATE_MASK
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#define CPSR_CUMMULATE_SHIFT PSR_CUMMULATE_SHIFT
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#define CPSR_OVERFLOW_MASK PSR_OVERFLOW_MASK
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#define CPSR_OVERFLOW_SHIFT PSR_OVERFLOW_SHIFT
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#define CPSR_CARRY_MASK PSR_CARRY_MASK
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#define CPSR_CARRY_SHIFT PSR_CARRY_SHIFT
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#define CPSR_ZERO_MASK PSR_ZERO_MASK
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#define CPSR_ZERO_SHIFT PSR_ZERO_SHIFT
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#define CPSR_NEGATIVE_MASK PSR_NEGATIVE_MASK
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#define CPSR_NEGATIVE_SHIFT PSR_NEGATIVE_SHIFT
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#define CPSR_NZCV_MASK PSR_NZCV_MASK
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#define CPSR_IT_MASK PSR_IT_MASK
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#define CPSR_USERBITS_MASK PSR_USERBITS_MASK
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#define CPSR_PRIVBITS_MASK PSR_PRIVBITS_MASK
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#define CPSR_ALLBITS_MASK PSR_ALLBITS_MASK
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