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25
mkrtos_user/server/net/inc/lan8270.h
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25
mkrtos_user/server/net/inc/lan8270.h
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#ifndef __LAN8720_H
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#define __LAN8720_H
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#include "sys.h"
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#include "stm32f4x7_eth.h"
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#define LAN8720_PHY_ADDRESS 0x00
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#define LAN8720_RST PDout(3)
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extern ETH_DMADESCTypeDef *DMARxDscrTab;
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extern ETH_DMADESCTypeDef *DMATxDscrTab;
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extern uint8_t *Rx_Buff;
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extern uint8_t *Tx_Buff;
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extern ETH_DMADESCTypeDef *DMATxDescToSet;
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extern ETH_DMADESCTypeDef *DMARxDescToGet;
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extern ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos;
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u8 LAN8720_Init(void);
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u8 LAN8720_Get_Speed(void);
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u8 ETH_MACDMA_Config(void);
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FrameTypeDef ETH_Rx_Packet(void);
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u8 ETH_Tx_Packet(u16 FrameLength);
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u32 ETH_GetCurrentTxBuffer(void);
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u8 ETH_Mem_Malloc(void);
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void ETH_Mem_Free(void);
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#endif
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227
mkrtos_user/server/net/src/lan8270.c
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mkrtos_user/server/net/src/lan8270.c
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#include "lan8720.h"
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#include "stm32f4x7_eth.h"
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#include <stm32f4xx.h>
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#include "u_sleep.h"
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#include <malloc.h>
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ETH_DMADESCTypeDef *DMARxDscrTab;
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ETH_DMADESCTypeDef *DMATxDscrTab;
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uint8_t *Rx_Buff;
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uint8_t *Tx_Buff;
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static void ETHERNET_NVICConfiguration(void);
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u8 LAN8720_Init(void)
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{
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u8 rval = 0;
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GPIO_InitTypeDef GPIO_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOD, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
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SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
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/*RMII
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ETH_MDIO -------------------------> PA2
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ETH_MDC --------------------------> PC1
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ETH_RMII_REF_CLK------------------> PA1
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ETH_RMII_CRS_DV ------------------> PA7
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ETH_RMII_RXD0 --------------------> PC4
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ETH_RMII_RXD1 --------------------> PC5
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ETH_RMII_TX_EN -------------------> PG11
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ETH_RMII_TXD0 --------------------> PG13
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ETH_RMII_TXD1 --------------------> PG14
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ETH_RESET-------------------------> PD3
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*/
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
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GPIO_Init(GPIOC, &GPIO_InitStructure);
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GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
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GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
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GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14;
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GPIO_Init(GPIOG, &GPIO_InitStructure);
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GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
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GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
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GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
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// RST
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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LAN8720_RST = 0;
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delay_ms(50);
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LAN8720_RST = 1;
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ETHERNET_NVICConfiguration();
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rval = ETH_MACDMA_Config();
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return !rval;
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}
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#include "u_intr.h"
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#define IRQ_THREAD_PRIO 2
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#define STACK_SIZE (1024)
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static obj_handler_t irq_obj;
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static __attribute__((aligned(8))) uint8_t stack0[STACK_SIZE];
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void ETH_IRQHandler(void);
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void ETHERNET_NVICConfiguration(void)
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{
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// NVIC_InitTypeDef NVIC_InitStructure;
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// NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
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// NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0X06;
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// NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0X00;
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// NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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// NVIC_Init(&NVIC_InitStructure);
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assert(u_intr_bind(ETH_IRQn, (u_irq_prio_t){.prio_p = 0X06, .prio_s = 0}, IRQ_THREAD_PRIO,
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stack0 + STACK_SIZE, NULL, ETH_IRQHandler, &irq_obj) >= 0);
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}
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u8 LAN8720_Get_Speed(void)
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{
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u8 speed;
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speed = ((ETH_ReadPHYRegister(0x00, 31) & 0x1C) >> 2);
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return speed;
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}
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u8 ETH_MACDMA_Config(void)
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{
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u8 rval;
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ETH_InitTypeDef ETH_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
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ETH_DeInit();
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ETH_SoftwareReset();
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while (ETH_GetSoftwareResetStatus() == SET)
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;
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ETH_StructInit(Ð_InitStructure);
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ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
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ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
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ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
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ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
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ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
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ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
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ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
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ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
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ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
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#ifdef CHECKSUM_BY_HARDWARE
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ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
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#endif
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ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
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ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
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ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
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ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
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ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
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ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
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ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
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ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
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ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
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ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
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ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
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rval = ETH_Init(Ð_InitStructure, LAN8720_PHY_ADDRESS);
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if (rval == ETH_SUCCESS)
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{
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ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);
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}
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return rval;
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}
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extern void lwip_pkt_handle(void);
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void ETH_IRQHandler(void)
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{
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while (ETH_GetRxPktSize(DMARxDescToGet) != 0)
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{
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lwip_pkt_handle();
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}
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ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
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ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
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}
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FrameTypeDef ETH_Rx_Packet(void)
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{
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u32 framelength = 0;
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FrameTypeDef frame = {0, 0};
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if ((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET)
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{
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frame.length = ETH_ERROR;
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if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
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{
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ETH->DMASR = ETH_DMASR_RBUS;
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ETH->DMARPDR = 0;
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}
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return frame;
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}
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if (((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (u32)RESET) &&
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((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (u32)RESET) &&
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((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (u32)RESET))
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{
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framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
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frame.buffer = DMARxDescToGet->Buffer1Addr;
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}
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else
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framelength = ETH_ERROR;
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frame.length = framelength;
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frame.descriptor = DMARxDescToGet;
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DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr);
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return frame;
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}
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u8 ETH_Tx_Packet(u16 FrameLength)
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{
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if ((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
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return ETH_ERROR;
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DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
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DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
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DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
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if ((ETH->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
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{
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ETH->DMASR = ETH_DMASR_TBUS;
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ETH->DMATPDR = 0;
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}
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DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr);
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return ETH_SUCCESS;
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}
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u32 ETH_GetCurrentTxBuffer(void)
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{
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return DMATxDescToSet->Buffer1Addr;
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}
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u8 ETH_Mem_Malloc(void)
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{
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DMARxDscrTab = malloc(ETH_RXBUFNB * sizeof(ETH_DMADESCTypeDef));
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DMATxDscrTab = malloc ETH_TXBUFNB * sizeof(ETH_DMADESCTypeDef));
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Rx_Buff = malloc(ETH_RX_BUF_SIZE * ETH_RXBUFNB);
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Tx_Buff = malloc(ETH_TX_BUF_SIZE * ETH_TXBUFNB);
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if (!DMARxDscrTab || !DMATxDscrTab || !Rx_Buff || !Tx_Buff)
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{
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ETH_Mem_Free();
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return 1;
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}
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return 0;
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}
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void ETH_Mem_Free(void)
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{
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free(DMARxDscrTab);
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free(DMATxDscrTab);
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free(Rx_Buff);
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free(Tx_Buff);
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}
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