lby/mkrtos-real
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

tmp

Browse Source
This commit is contained in:
zhangzheng
2024-01-14 18:28:00 +08:00
parent e395af682b
commit 57fb11ec87
12 changed files with 152 additions and 857 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
mkrtos_user/server/net/inc/lan8270.h
View File

@@ -1,6 +1,6 @@
#ifndef __LAN8720_H
#define __LAN8720_H
#include "sys.h"
#include "mk_sys.h"
#include "stm32f4x7_eth.h"
#define LAN8720_PHY_ADDRESS 0x00

69
mkrtos_user/server/net/inc/mk_sys.h Executable file
View File

@@ -0,0 +1,69 @@
#ifndef __SYS_H
#define __SYS_H
#include <stm32f4xx.h>
#include <stm32f4xx_conf.h>
//IO口操作宏定义
#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
//IO口地址映射
#define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C
#define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C
#define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C
#define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C
#define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C
#define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C
#define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C
#define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808
#define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08
#define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008
#define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408
#define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808
#define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08
#define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08
//IO口操作,只对单一的IO口!
//确保n的值小于16!
#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //输出
#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //输入
#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //输出
#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //输入
#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //输出
#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //输入
#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //输出
#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //输入
#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //输出
#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //输入
#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //输出
#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //输入
#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //输出
#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //输入
//Ex_NVIC_Config专用定义
#define GPIO_A 0
#define GPIO_B 1
#define GPIO_C 2
#define GPIO_D 3
#define GPIO_E 4
#define GPIO_F 5
#define GPIO_G 6
#define FTIR 1 //下降沿触发
#define RTIR 2 //上升沿触发
//JTAG模式设置定义
#define JTAG_SWD_DISABLE 0X02
#define SWD_ENABLE 0X01
#define JTAG_SWD_ENABLE 0X00
void jump2kernel(void);
#endif

3
mkrtos_user/server/net/inc/stm32f4x7_eth.h
View File

@@ -36,7 +36,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4x7_eth_conf.h"
/** @addtogroup STM32F4x7_ETH_Driver
* @{
*/
@@ -48,7 +47,7 @@
/**
* @brief ETH MAC Init structure definition
* @note The user should not configure all the ETH_InitTypeDef structure's fields.
* By calling the ETH_StructInit function the structure<72>s fields are set to their default values.
* By calling the ETH_StructInit function the structure<72>s fields are set to their default values.
* Only the parameters that will be set to a non-default value should be configured.
*/
typedef struct {

89
mkrtos_user/server/net/inc/stm32f4x7_eth_bsp.h
View File

@@ -1,89 +0,0 @@
/**
******************************************************************************
* @file stm32f4x7_eth_bsp.h
* @author MCD Application Team
* @version V1.1.0
* @date 31-July-2013
* @brief Header for stm32f4x7_eth_bsp.c file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4x7_ETH_BSP_H
#define __STM32F4x7_ETH_BSP_H
#ifdef __cplusplus
extern "C"
{
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
#include "stm32f4x7_eth_conf.h"
#include "lwip/netif.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#define DP83848_PHY_ADDRESS ((uint16_t)0x01)
/* Specific defines for EXTI line, used to manage Ethernet link status */
#define ETH_LINK_EXTI_LINE EXTI_Line14
#define ETH_LINK_EXTI_PORT_SOURCE EXTI_PortSourceGPIOB
#define ETH_LINK_EXTI_PIN_SOURCE EXTI_PinSource14
#define ETH_LINK_EXTI_IRQn EXTI15_10_IRQn
/* PB14 */
#define ETH_LINK_PIN GPIO_Pin_14
#define ETH_LINK_GPIO_PORT GPIOB
#define ETH_LINK_GPIO_CLK RCC_AHB1Periph_GPIOB
/* Ethernet Flags for EthStatus variable */
#define ETH_INIT_FLAG 0x01 /* Ethernet Init Flag */
#define ETH_LINK_FLAG 0x10 /* Ethernet Link Flag */
/* Uncomment SERIAL_DEBUG to enables retarget of printf to serial port (COM1 on STM32 evalboard)
for debug purpose */
// #define MII_MODE
/* Uncomment the define below to clock the PHY from external 25MHz crystal (only for MII mode) */
#ifdef MII_MODE
#define PHY_CLOCK_MCO
#endif
extern __IO uint32_t LocalTime;
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void ETH_BSP_Config(void);
void ETH_NVIC_Config(void);
uint32_t Eth_Link_PHYITConfig(uint16_t PHYAddress);
void Eth_Link_EXTIConfig(void);
void Eth_Link_ITHandler(uint16_t PHYAddress);
void ETH_link_callback(struct netif *netif);
void Time_Update(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4x7_ETH_BSP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

209
mkrtos_user/server/net/src/ethernetif.c
View File

@@ -53,6 +53,7 @@
#include "ethernetif.h"
#include "stm32f4x7_eth.h"
#include "lan8270.h"
#include <string.h>
#define netifMTU (1500)
@@ -68,20 +69,20 @@
static struct netif *s_pxNetIf = NULL;
// xSemaphoreHandle s_xSemaphore = NULL;
int s_xSemaphore = 0;
// int s_xSemaphore = 0;
/* Ethernet Rx & Tx DMA Descriptors */
extern ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
// /* Ethernet Rx & Tx DMA Descriptors */
// extern ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
/* Ethernet Receive buffers */
extern uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];
// /* Ethernet Receive buffers */
// extern uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];
/* Ethernet Transmit buffers */
extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];
// /* Ethernet Transmit buffers */
// extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];
/* Global pointers to track current transmit and receive descriptors */
extern ETH_DMADESCTypeDef *DMATxDescToSet;
extern ETH_DMADESCTypeDef *DMARxDescToGet;
// /* Global pointers to track current transmit and receive descriptors */
// extern ETH_DMADESCTypeDef *DMATxDescToSet;
// extern ETH_DMADESCTypeDef *DMARxDescToGet;
/* Global pointer for last received frame infos */
extern ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos;
@@ -115,24 +116,17 @@ static void low_level_init(struct netif *netif)
netif->mtu = 1500;
/* Accept broadcast address and ARP traffic */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
s_pxNetIf = netif;
/* create binary semaphore used for informing ethernetif of frame reception */
// if (s_xSemaphore == NULL)
// {
// vSemaphoreCreateBinary(s_xSemaphore);
// xSemaphoreTake(s_xSemaphore, 0);
// }
/* initialize MAC address in ethernet MAC */
ETH_MACAddressConfig(ETH_MAC_Address0, netif->hwaddr);
/* Initialize Tx Descriptors list: Chain Mode */
ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
ETH_DMATxDescChainInit(DMATxDscrTab, Tx_Buff, ETH_TXBUFNB);
/* Initialize Rx Descriptors list: Chain Mode */
ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
ETH_DMARxDescChainInit(DMARxDscrTab, Rx_Buff, ETH_RXBUFNB);
/* Enable Ethernet Rx interrrupt */
{
@@ -152,10 +146,6 @@ static void low_level_init(struct netif *netif)
}
#endif
/* create the task that handles the ETH_MAC */
// xTaskCreate(ethernetif_input, (signed char *)"Eth_if", netifINTERFACE_TASK_STACK_SIZE, NULL,
// netifINTERFACE_TASK_PRIORITY, NULL);
/* Enable MAC and DMA transmission and reception */
ETH_Start();
}
@@ -178,75 +168,18 @@ static void low_level_init(struct netif *netif)
static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
// static xSemaphoreHandle xTxSemaphore = NULL;
u8 res;
struct pbuf *q;
u8 *buffer;
__IO ETH_DMADESCTypeDef *DmaTxDesc;
uint16_t framelength = 0;
uint32_t bufferoffset = 0;
uint32_t byteslefttocopy = 0;
uint32_t payloadoffset = 0;
// if (xTxSemaphore == NULL)
// {
// vSemaphoreCreateBinary(xTxSemaphore);
// }
// if (xSemaphoreTake(xTxSemaphore, netifGUARD_BLOCK_TIME))
// {
DmaTxDesc = DMATxDescToSet;
buffer = (u8 *)(DmaTxDesc->Buffer1Addr);
bufferoffset = 0;
int l = 0;
u8 *buffer = (u8 *)ETH_GetCurrentTxBuffer();
for (q = p; q != NULL; q = q->next)
{
if ((DmaTxDesc->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
{
goto error;
}
/* Get bytes in current lwIP buffer */
byteslefttocopy = q->len;
payloadoffset = 0;
/* Check if the length of data to copy is bigger than Tx buffer size*/
while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE)
{
/* Copy data to Tx buffer*/
memcpy((u8_t *)((u8_t *)buffer + bufferoffset), (u8_t *)((u8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
/* Point to next descriptor */
DmaTxDesc = (ETH_DMADESCTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
/* Check if the buffer is available */
if ((DmaTxDesc->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
{
goto error;
}
buffer = (u8 *)(DmaTxDesc->Buffer1Addr);
byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
bufferoffset = 0;
}
/* Copy the remaining bytes */
memcpy((u8_t *)((u8_t *)buffer + bufferoffset), (u8_t *)((u8_t *)q->payload + payloadoffset), byteslefttocopy);
bufferoffset = bufferoffset + byteslefttocopy;
framelength = framelength + byteslefttocopy;
memcpy((u8_t *)&buffer[l], q->payload, q->len);
l = l + q->len;
}
/* Prepare transmit descriptors to give to DMA*/
ETH_Prepare_Transmit_Descriptors(framelength);
/* Give semaphore and exit */
error:
// xSemaphoreGive(xTxSemaphore);
// }
res = ETH_Tx_Packet(l);
if (res == ETH_ERROR)
return ERR_MEM;
return ERR_OK;
}
@@ -260,79 +193,28 @@ error:
*/
static struct pbuf *low_level_input(struct netif *netif)
{
struct pbuf *p = NULL, *q;
u32_t len;
struct pbuf *p, *q;
u16_t len;
int l = 0;
FrameTypeDef frame;
u8 *buffer;
__IO ETH_DMADESCTypeDef *DMARxDesc;
uint32_t bufferoffset = 0;
uint32_t payloadoffset = 0;
uint32_t byteslefttocopy = 0;
uint32_t i = 0;
/* get received frame */
frame = ETH_Get_Received_Frame_interrupt();
/* Obtain the size of the packet and put it into the "len" variable. */
p = NULL;
frame = ETH_Rx_Packet();
len = frame.length;
buffer = (u8 *)frame.buffer;
if (len > 0)
{
/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
}
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
if (p != NULL)
{
DMARxDesc = frame.descriptor;
bufferoffset = 0;
for (q = p; q != NULL; q = q->next)
{
byteslefttocopy = q->len;
payloadoffset = 0;
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE)
{
/* Copy data to pbuf*/
memcpy((u8_t *)((u8_t *)q->payload + payloadoffset), (u8_t *)((u8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
/* Point to next descriptor */
DMARxDesc = (ETH_DMADESCTypeDef *)(DMARxDesc->Buffer2NextDescAddr);
buffer = (unsigned char *)(DMARxDesc->Buffer1Addr);
byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
bufferoffset = 0;
}
/* Copy remaining data in pbuf */
memcpy((u8_t *)((u8_t *)q->payload + payloadoffset), (u8_t *)((u8_t *)buffer + bufferoffset), byteslefttocopy);
bufferoffset = bufferoffset + byteslefttocopy;
memcpy((u8_t *)q->payload, (u8_t *)&buffer[l], q->len);
l = l + q->len;
}
/* Release descriptors to DMA */
DMARxDesc = frame.descriptor;
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
for (i = 0; i < DMA_RX_FRAME_infos->Seg_Count; i++)
{
DMARxDesc->Status = ETH_DMARxDesc_OWN;
DMARxDesc = (ETH_DMADESCTypeDef *)(DMARxDesc->Buffer2NextDescAddr);
}
/* Clear Segment_Count */
DMA_RX_FRAME_infos->Seg_Count = 0;
/* added for test*/
}
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
frame.descriptor->Status = ETH_DMARxDesc_OWN;
if ((ETH->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
{
/* Clear RBUS ETHERNET DMA flag */
ETH->DMASR = ETH_DMASR_RBUS;
/* Resume DMA reception */
ETH->DMARPDR = 0;
}
return p;
@@ -351,29 +233,18 @@ void ethernetif_input(void *pvParameters)
{
struct pbuf *p;
for (;;)
// TRY_GET_NEXT_FRAME:
p = low_level_input(s_pxNetIf);
if (p != NULL)
{
// if (xSemaphoreTake(s_xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT) == pdTRUE)
// {
if (s_xSemaphore >= 0)
if (ERR_OK != s_pxNetIf->input(p, s_pxNetIf))
{
s_xSemaphore--;
TRY_GET_NEXT_FRAME:
p = low_level_input(s_pxNetIf);
if (p != NULL)
{
if (ERR_OK != s_pxNetIf->input(p, s_pxNetIf))
{
pbuf_free(p);
}
else
{
goto TRY_GET_NEXT_FRAME;
}
}
pbuf_free(p);
}
else
{
// goto TRY_GET_NEXT_FRAME;
}
u_sleep_ms(1);
// }
}
}

2
mkrtos_user/server/net/src/heap_stack.c
View File

@@ -1,5 +1,5 @@
#define HEAP_SIZE 8192
#define HEAP_SIZE 32*1024
#define STACK_SIZE (2048)
#if defined(__CC_ARM)

23
mkrtos_user/server/net/src/lan8270.c
View File

@@ -1,8 +1,9 @@
#include "lan8720.h"
#include "lan8270.h"
#include "stm32f4x7_eth.h"
#include <stm32f4xx.h>
#include "u_sleep.h"
#include <malloc.h>
#include <assert.h>
ETH_DMADESCTypeDef *DMARxDscrTab;
ETH_DMADESCTypeDef *DMATxDscrTab;
@@ -65,7 +66,7 @@ u8 LAN8720_Init(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
LAN8720_RST = 0;
delay_ms(50);
u_sleep_ms(50);
LAN8720_RST = 1;
ETHERNET_NVICConfiguration();
rval = ETH_MACDMA_Config();
@@ -148,12 +149,20 @@ u8 ETH_MACDMA_Config(void)
extern void lwip_pkt_handle(void);
void ETH_IRQHandler(void)
{
while (ETH_GetRxPktSize(DMARxDescToGet) != 0)
msg_tag_t tag = uirq_wait(irq_obj, 0);
if (msg_tag_get_val(tag) >= 0)
{
lwip_pkt_handle();
if (DMARxDescToGet)
{
while (ETH_GetRxPktSize(DMARxDescToGet) != 0)
{
lwip_pkt_handle();
}
}
ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
}
ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
uirq_ack(irq_obj, ETH_IRQn);
}
FrameTypeDef ETH_Rx_Packet(void)
@@ -207,7 +216,7 @@ u32 ETH_GetCurrentTxBuffer(void)
u8 ETH_Mem_Malloc(void)
{
DMARxDscrTab = malloc(ETH_RXBUFNB * sizeof(ETH_DMADESCTypeDef));
DMATxDscrTab = malloc ETH_TXBUFNB * sizeof(ETH_DMADESCTypeDef));
DMATxDscrTab = malloc(ETH_TXBUFNB * sizeof(ETH_DMADESCTypeDef));
Rx_Buff = malloc(ETH_RX_BUF_SIZE * ETH_RXBUFNB);
Tx_Buff = malloc(ETH_TX_BUF_SIZE * ETH_TXBUFNB);
if (!DMARxDscrTab || !DMATxDscrTab || !Rx_Buff || !Tx_Buff)

10
mkrtos_user/server/net/src/main.c
View File

@@ -3,10 +3,10 @@
#include "netconf.h"
#include "u_drv.h"
#include "stm32f4x7_eth.h"
#include "stm32f4x7_eth_bsp.h"
#include <unistd.h>
#include <stdio.h>
#include "libc.h"
#include "lan8270.h"
int main(int args, char *argv[])
{
struct __libc *lc = &libc;
@@ -14,16 +14,18 @@ int main(int args, char *argv[])
printf("libc:0x%x\n", lc);
u_drv_init();
cons_write_str("net init..\n");
ETH_BSP_Config();
ETH_Mem_Malloc();
LAN8720_Init();
net_init();
cons_write_str("net start success..\n");
while (1)
{
// if (ETH_CheckFrameReceived())
// {
/* process received ethernet packet */
LwIP_Pkt_Handle();
/* process received ethernet packet */
// LwIP_Pkt_Handle();
// }
sleep(1);
}
return 0;
}

21
mkrtos_user/server/net/src/netconf.c
View File

@@ -49,7 +49,7 @@
#include "ethernetif.h"
#include "lwip/netif.h"
#include "stm32f4x7_eth.h"
#include "stm32f4x7_eth_bsp.h"
// #include "stm32f4x7_eth_bsp.h"
#include <stdio.h>
#include "cons_cli.h"
#include "ethernetif.h"
@@ -63,7 +63,7 @@ uint32_t DHCPfineTimer = 0;
uint32_t DHCPcoarseTimer = 0;
DHCP_State_TypeDef DHCP_state = DHCP_START;
#endif
extern __IO uint32_t EthStatus;
extern __IO uint32_t EthStatus;
/**
* @brief Initializes the lwIP stack
* @param None
@@ -114,12 +114,12 @@ void net_init(void)
The init function pointer must point to a initialization function for
your ethernet netif interface. The following code illustrates it's use.*/
sys_lock_tcpip_core();
netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, &ethernetif_init, &ethernet_input);
struct netif *netif_flag = netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, &ethernetif_init, &ethernet_input);
/* Registers the default network interface.*/
netif_set_default(&gnetif);
if (EthStatus == (ETH_INIT_FLAG | ETH_LINK_FLAG))
if (netif_flag)
{
/* Set Ethernet link flag */
gnetif.flags |= NETIF_FLAG_LINK_UP;
@@ -140,22 +140,17 @@ void net_init(void)
#ifdef USE_DHCP
DHCP_state = DHCP_LINK_DOWN;
#endif /* USE_DHCP */
#endif /* USE_DHCP */
/* Set the LCD Text Color */
}
/* Set the link callback function, this function is called on change of link status*/
netif_set_link_callback(&gnetif, ETH_link_callback);
// netif_set_link_callback(&gnetif, ETH_link_callback);
sys_unlock_tcpip_core();
}
void ethernetif_input(void *pvParameters);
/**
* @brief Called when a frame is received
* @param None
* @retval None
*/
void LwIP_Pkt_Handle(void)
// 用于以太网中断调用
void lwip_pkt_handle(void)
{
/* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */
ethernetif_input(&gnetif);
}

14
mkrtos_user/server/net/src/stm32f4x7_eth.c
View File

@@ -84,10 +84,12 @@ uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */
uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */
#elif defined (__GNUC__) /*!< GNU Compiler */
ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Rx DMA Descriptor */
ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Tx DMA Descriptor */
uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Receive Buffer */
uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Transmit Buffer */
// ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Rx DMA Descriptor */
// ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Tx DMA Descriptor */
// uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Receive Buffer */
// uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Transmit Buffer */
#elif defined (__TASKING__) /*!< TASKING Compiler */
__align(4)
@@ -1913,7 +1915,7 @@ FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
}
/**
* @brief Clears the ETHERNET<45>s DMA pending flag.
* @brief Clears the ETHERNET<45>s DMA pending flag.
* @param ETH_DMA_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
@@ -2025,7 +2027,7 @@ ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
}
/**
* @brief Clears the ETHERNET<45>s DMA IT pending bit.
* @brief Clears the ETHERNET<45>s DMA IT pending bit.
* @param ETH_DMA_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg ETH_DMA_IT_NIS : Normal interrupt summary

564
mkrtos_user/server/net/src/stm32f4x7_eth_bsp.c
View File

@@ -1,564 +0,0 @@
/**
******************************************************************************
* @file stm32f4x7_eth_bsp.c
* @author MCD Application Team
* @version V1.1.0
* @date 31-July-2013
* @brief STM32F4x7 Ethernet hardware configuration.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lwip/opt.h"
#include "stm32f4x7_eth.h"
#include "stm32f4x7_eth_bsp.h"
#include "lwip/netif.h"
#include "netconf.h"
#include "lwip/dhcp.h"
#include "u_intr.h"
#include "u_prot.h"
#include <assert.h>
/* Private functions ---------------------------------------------------------*/
/**
* @brief ETH_BSP_Config
* @param None
* @retval None
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
ETH_InitTypeDef ETH_InitStructure;
__IO uint32_t EthStatus = 0;
__IO uint32_t LocalTime = 0;
extern struct netif gnetif;
#ifdef USE_DHCP
extern __IO uint8_t DHCP_state;
#endif /* LWIP_DHCP */
/* Private function prototypes -----------------------------------------------*/
static void ETH_GPIO_Config(void);
static void ETH_MACDMA_Config(void);
/* Private functions ---------------------------------------------------------*/
/**
* @brief ETH_BSP_Config
* @param None
* @retval None
*/
void ETH_BSP_Config(void)
{
RCC_ClocksTypeDef RCC_Clocks;
/***************************************************************************
NOTE:
When using Systick to manage the delay in Ethernet driver, the Systick
must be configured before Ethernet initialization and, the interrupt
priority should be the highest one.
*****************************************************************************/
/* Configure Systick clock source as HCLK */
// SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
/* SystTick configuration: an interrupt every 10ms */
// RCC_GetClocksFreq(&RCC_Clocks);
// SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);
/* Set Systick interrupt priority to 0*/
// NVIC_SetPriority(SysTick_IRQn, 0);
/* Configure the GPIO ports for ethernet pins */
ETH_GPIO_Config();
/* Config NVIC for Ethernet */
ETH_NVIC_Config();
/* Configure the Ethernet MAC/DMA */
ETH_MACDMA_Config();
/* Read PHY status register: Get Ethernet link status */
if (ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR) & 1)
{
EthStatus |= ETH_LINK_FLAG;
}
/* Configure the PHY to generate an interrupt on change of link status */
Eth_Link_PHYITConfig(DP83848_PHY_ADDRESS);
/* Configure the EXTI for Ethernet link status. */
Eth_Link_EXTIConfig();
}
#define IRQ_THREAD_PRIO 2
#define STACK_SIZE (1024)
static obj_handler_t irq_obj;
static __attribute__((aligned(8))) uint8_t stack0[STACK_SIZE];
extern int s_xSemaphore;
void ETH_IRQHandler(void)
{
while (1)
{
msg_tag_t tag = uirq_wait(irq_obj, 0);
if (msg_tag_get_val(tag) >= 0)
{
// portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* Frame received */
if (ETH_GetDMAFlagStatus(ETH_DMA_FLAG_R) == SET)
{
/* Give the semaphore to wakeup LwIP task */
// xSemaphoreGiveFromISR(s_xSemaphore, &xHigherPriorityTaskWoken);
s_xSemaphore++;
}
/* Clear the interrupt flags. */
/* Clear the Eth DMA Rx IT pending bits */
ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
/* Switch tasks if necessary. */
// if (xHigherPriorityTaskWoken != pdFALSE)
// {
// portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
// }
}
uirq_ack(irq_obj, ETH_IRQn);
}
}
void ETH_NVIC_Config(void)
{
// NVIC_InitTypeDef NVIC_InitStructure;
// /* Enable the Ethernet global Interrupt */
// NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
// NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 12;
// NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
// NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
// NVIC_Init(&NVIC_InitStructure);
assert(u_intr_bind(ETH_IRQn, (u_irq_prio_t){.prio_p = 12, .prio_s = 0}, IRQ_THREAD_PRIO,
stack0 + STACK_SIZE, NULL, ETH_IRQHandler, &irq_obj) >= 0);
}
/**
* @brief Configures the Ethernet Interface
* @param None
* @retval None
*/
static void ETH_MACDMA_Config(void)
{
/* Enable ETHERNET clock */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
RCC_AHB1Periph_ETH_MAC_Rx,
ENABLE);
/* Reset ETHERNET on AHB Bus */
ETH_DeInit();
/* Software reset */
ETH_SoftwareReset();
/* Wait for software reset */
while (ETH_GetSoftwareResetStatus() == SET)
;
/* ETHERNET Configuration --------------------------------------------------*/
/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
ETH_StructInit(&ETH_InitStructure);
/* Fill ETH_InitStructure parametrs */
/*------------------------ MAC -----------------------------------*/
ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
// ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
// ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
// ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
#ifdef CHECKSUM_BY_HARDWARE
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
#endif
/*------------------------ DMA -----------------------------------------*/
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
/* Configure Ethernet */
EthStatus = ETH_Init(&ETH_InitStructure, DP83848_PHY_ADDRESS);
}
/**
* @brief Configures the different GPIO ports.
* @param None
* @retval None
*/
void ETH_GPIO_Config(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable GPIOs clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOI |
RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH |
RCC_AHB1Periph_GPIOF,
ENABLE);
/* Enable SYSCFG clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
/* Configure MCO (PA8) */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* MII/RMII Media interface selection --------------------------------------*/
#ifdef MII_MODE /* Mode MII with STM324xG-EVAL */
#ifdef PHY_CLOCK_MCO
/* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY */
RCC_MCO1Config(RCC_MCO1Source_HSE, RCC_MCO1Div_1);
#endif /* PHY_CLOCK_MCO */
SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_MII);
#elif defined RMII_MODE /* Mode RMII with STM324xG-EVAL */
SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
#endif
/* Ethernet pins configuration ************************************************/
/*
ETH_MDIO -------------------------> PA2
ETH_MDC --------------------------> PC1
ETH_PPS_OUT ----------------------> PB5
ETH_MII_CRS ----------------------> PH2
ETH_MII_COL ----------------------> PH3
ETH_MII_RX_ER --------------------> PI10
ETH_MII_RXD2 ---------------------> PH6
ETH_MII_RXD3 ---------------------> PH7
ETH_MII_TX_CLK -------------------> PC3
ETH_MII_TXD2 ---------------------> PC2
ETH_MII_TXD3 ---------------------> PB8
ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1
ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7
ETH_MII_RXD0/ETH_RMII_RXD0 -------> PC4
ETH_MII_RXD1/ETH_RMII_RXD1 -------> PC5
ETH_MII_TX_EN/ETH_RMII_TX_EN -----> PG11
ETH_MII_TXD0/ETH_RMII_TXD0 -------> PG13
ETH_MII_TXD1/ETH_RMII_TXD1 -------> PG14
*/
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
/* Configure PB11 and PB12 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);
/* Configure PC1, PC2, PC3, PC4 and PC5 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
/* Configure PG11, PG14 and PG13 */ /*
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14;
GPIO_Init(GPIOG, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH); */
/* Configure PH2, PH3, PH6, PH7 */ /*
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 | GPIO_Pin_7;
GPIO_Init(GPIOH, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOH, GPIO_PinSource2, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOH, GPIO_PinSource3, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOH, GPIO_PinSource6, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOH, GPIO_PinSource7, GPIO_AF_ETH); */
/* Configure PI10 */ /*
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
GPIO_Init(GPIOI, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOI, GPIO_PinSource10, GPIO_AF_ETH); */
}
/**
* @brief Configure the PHY to generate an interrupt on change of link status.
* @param PHYAddress: external PHY address
* @retval None
*/
uint32_t Eth_Link_PHYITConfig(uint16_t PHYAddress)
{
uint16_t tmpreg = 0;
/* Read MICR register */
tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_MICR);
/* Enable output interrupt events to signal via the INT pin */
tmpreg |= (uint16_t)(PHY_MICR_INT_EN | PHY_MICR_INT_OE);
if (!(ETH_WritePHYRegister(PHYAddress, PHY_MICR, tmpreg)))
{
/* Return ERROR in case of write timeout */
return ETH_ERROR;
}
/* Read MISR register */
tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_MISR);
/* Enable Interrupt on change of link status */
tmpreg |= (uint16_t)PHY_MISR_LINK_INT_EN;
if (!(ETH_WritePHYRegister(PHYAddress, PHY_MISR, tmpreg)))
{
/* Return ERROR in case of write timeout */
return ETH_ERROR;
}
/* Return SUCCESS */
return ETH_SUCCESS;
}
#define IRQ_THREAD_PRIO2 2
#define STACK_SIZE2 (512 + 128)
static obj_handler_t irq_line_obj;
static __attribute__((aligned(8))) uint8_t stack1[STACK_SIZE2];
void EXTI15_10_IRQHandler(void)
{
while (1)
{
msg_tag_t tag = uirq_wait(irq_line_obj, 0);
if (msg_tag_get_val(tag) >= 0)
{
if (EXTI_GetITStatus(ETH_LINK_EXTI_LINE) != RESET)
{
Eth_Link_ITHandler(DP83848_PHY_ADDRESS);
/* Clear interrupt pending bit */
EXTI_ClearITPendingBit(ETH_LINK_EXTI_LINE);
}
}
uirq_ack(irq_line_obj, EXTI15_10_IRQn);
}
}
/**
* @brief EXTI configuration for Ethernet link status.
* @param PHYAddress: external PHY address
* @retval None
*/
void Eth_Link_EXTIConfig(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
EXTI_InitTypeDef EXTI_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
/* Enable the INT (PB14) Clock */
RCC_AHB1PeriphClockCmd(ETH_LINK_GPIO_CLK, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
/* Configure INT pin as input */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitStructure.GPIO_Pin = ETH_LINK_PIN;
GPIO_Init(ETH_LINK_GPIO_PORT, &GPIO_InitStructure);
/* Connect EXTI Line to INT Pin */
SYSCFG_EXTILineConfig(ETH_LINK_EXTI_PORT_SOURCE, ETH_LINK_EXTI_PIN_SOURCE);
/* Configure EXTI line */
EXTI_InitStructure.EXTI_Line = ETH_LINK_EXTI_LINE;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
/* Enable and set the EXTI interrupt to priority 1*/
// NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn;
// NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
// NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
// NVIC_Init(&NVIC_InitStructure);
assert(u_intr_bind(EXTI15_10_IRQn, (u_irq_prio_t){.prio_p = 1, .prio_s = 0}, IRQ_THREAD_PRIO2,
stack1 + STACK_SIZE2, NULL, EXTI15_10_IRQHandler, &irq_line_obj) >= 0);
}
/**
* @brief This function handles Ethernet link status.
* @param None
* @retval None
*/
void Eth_Link_ITHandler(uint16_t PHYAddress)
{
/* Check whether the link interrupt has occurred or not */
if (((ETH_ReadPHYRegister(PHYAddress, PHY_MISR)) & PHY_LINK_STATUS) != 0)
{
if ((ETH_ReadPHYRegister(PHYAddress, PHY_SR) & 1))
{
netif_set_link_up(&gnetif);
}
else
{
netif_set_link_down(&gnetif);
}
}
}
/**
* @brief Link callback function, this function is called on change of link status.
* @param The network interface
* @retval None
*/
void ETH_link_callback(struct netif *netif)
{
__IO uint32_t timeout = 0;
uint32_t tmpreg;
uint16_t RegValue;
ip4_addr_t ipaddr;
ip4_addr_t netmask;
ip4_addr_t gw;
#ifndef USE_DHCP
uint8_t iptab[4] = {0};
uint8_t iptxt[20];
#endif /* USE_DHCP */
if (netif_is_link_up(netif))
{
/* Restart the auto-negotiation */
if (ETH_InitStructure.ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
{
/* Reset Timeout counter */
timeout = 0;
/* Enable auto-negotiation */
ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_BCR, PHY_AutoNegotiation);
/* Wait until the auto-negotiation will be completed */
do
{
timeout++;
} while (!(ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
/* Reset Timeout counter */
timeout = 0;
/* Read the result of the auto-negotiation */
RegValue = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_SR);
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if ((RegValue & PHY_DUPLEX_STATUS) != (uint16_t)RESET)
{
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
}
else
{
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
ETH_InitStructure.ETH_Mode = ETH_Mode_HalfDuplex;
}
/* Configure the MAC with the speed fixed by the auto-negotiation process */
if (RegValue & PHY_SPEED_STATUS)
{
/* Set Ethernet speed to 10M following the auto-negotiation */
ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
}
else
{
/* Set Ethernet speed to 100M following the auto-negotiation */
ETH_InitStructure.ETH_Speed = ETH_Speed_100M;
}
/*------------------------ ETHERNET MACCR Re-Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = ETH->MACCR;
/* Set the FES bit according to ETH_Speed value */
/* Set the DM bit according to ETH_Mode value */
tmpreg |= (uint32_t)(ETH_InitStructure.ETH_Speed | ETH_InitStructure.ETH_Mode);
/* Write to ETHERNET MACCR */
ETH->MACCR = (uint32_t)tmpreg;
_eth_delay_(ETH_REG_WRITE_DELAY);
tmpreg = ETH->MACCR;
ETH->MACCR = tmpreg;
}
/* Restart MAC interface */
ETH_Start();
#ifdef USE_DHCP
ipaddr.addr = 0;
netmask.addr = 0;
gw.addr = 0;
DHCP_state = DHCP_START;
#else
IP4_ADDR(&ipaddr, IP_ADDR0, IP_ADDR1, IP_ADDR2, IP_ADDR3);
IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1, NETMASK_ADDR2, NETMASK_ADDR3);
IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3);
#endif /* USE_DHCP */
netif_set_addr(&gnetif, &ipaddr, &netmask, &gw);
/* When the netif is fully configured this function must be called.*/
netif_set_up(&gnetif);
}
else
{
ETH_Stop();
#ifdef USE_DHCP
DHCP_state = DHCP_LINK_DOWN;
dhcp_stop(netif);
#endif /* USE_DHCP */
/* When the netif link is down this function must be called.*/
netif_set_down(&gnetif);
}
}
void Time_Update(void)
{
LocalTime += 1000;
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/