Zhong,Fangjian ffe4be84b1 [arch][x86] bug fix in TSS descriptor base address ...

In 64-bit mode, the TSS descriptor is expanded to 16 bytes.
Currently, high 32-bit of TSS base address is set to be zero.
Updte descriptor structure definition, add high 32-bit high adress
and reserved bit.

Signed-off-by: Zhong,Fangjian <fangjian.zhong@intel.com>

2017-10-23 00:20:04 -07:00

..

arm

[arch][arm] disable alignment aborts

2017-02-06 18:54:11 -08:00

arm64

[arch][arm64] change CACHE_LINE to 64 for cortex a53,57 and 72

2017-06-05 10:41:45 -07:00

microblaze

[spelling] spelling-fixes. (not external/)

2016-08-25 17:30:34 -07:00

mips

[spelling] spelling-fixes. (not external/)

2016-08-25 17:30:34 -07:00

or1k

[spelling] spelling-fixes. (not external/)

2016-08-25 17:30:34 -07:00

x86

[arch][x86] bug fix in TSS descriptor base address

2017-10-23 00:20:04 -07:00