fdc08a8446
Very little needed to port except to conditionalize some assembly in the context switch and exception code. Mostly needed to move build system stuff around and add a new project.
117 lines
3.0 KiB
ArmAsm
117 lines
3.0 KiB
ArmAsm
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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// based on 32 or 64bit register widths, select the 32 or 64 bit
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// wide load/stores
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#if __riscv_xlen == 32
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#define REGOFF(x) ((x) * 4)
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#define STR sw
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#define LDR lw
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#else
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#define REGOFF(x) ((x) * 8)
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#define STR sd
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#define LDR ld
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#endif
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/* void riscv_context_switch(
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struct riscv_context_switch_frame *oldcs,
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struct riscv_context_switch_frame *newcs); */
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FUNCTION(riscv_context_switch)
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# a0 = oldcs
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# a1 = newcs
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STR ra, REGOFF(0)(a0)
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STR sp, REGOFF(1)(a0)
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STR tp, REGOFF(2)(a0)
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STR s0, REGOFF(3)(a0)
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STR s1, REGOFF(4)(a0)
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STR s2, REGOFF(5)(a0)
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STR s3, REGOFF(6)(a0)
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STR s4, REGOFF(7)(a0)
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STR s5, REGOFF(8)(a0)
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STR s6, REGOFF(9)(a0)
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STR s7, REGOFF(10)(a0)
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STR s8, REGOFF(11)(a0)
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STR s9, REGOFF(12)(a0)
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STR s10, REGOFF(13)(a0)
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STR s11, REGOFF(14)(a0)
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LDR s11, REGOFF(14)(a1)
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LDR s10, REGOFF(13)(a1)
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LDR s9, REGOFF(12)(a1)
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LDR s8, REGOFF(11)(a1)
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LDR s7, REGOFF(10)(a1)
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LDR s6, REGOFF(9)(a1)
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LDR s5, REGOFF(8)(a1)
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LDR s4, REGOFF(7)(a1)
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LDR s3, REGOFF(6)(a1)
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LDR s2, REGOFF(5)(a1)
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LDR s1, REGOFF(4)(a1)
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LDR s0, REGOFF(3)(a1)
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LDR tp, REGOFF(2)(a1)
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LDR sp, REGOFF(1)(a1)
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LDR ra, REGOFF(0)(a1)
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ret
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/* top level exception handler for riscv in non vectored mode */
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.balign 4
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FUNCTION(riscv_exception_entry)
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/* dump all the callee trashed regs on the stack */
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addi sp, sp, -REGOFF(20) // subtract a multiple of 16 to align the stack in 32bit
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STR t6, REGOFF(17)(sp)
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STR t5, REGOFF(16)(sp)
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STR t4, REGOFF(15)(sp)
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STR t3, REGOFF(14)(sp)
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STR t2, REGOFF(13)(sp)
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STR t1, REGOFF(12)(sp)
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STR t0, REGOFF(11)(sp)
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STR a7, REGOFF(10)(sp)
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STR a6, REGOFF(9)(sp)
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STR a5, REGOFF(8)(sp)
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STR a4, REGOFF(7)(sp)
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STR a3, REGOFF(6)(sp)
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STR a2, REGOFF(5)(sp)
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STR a1, REGOFF(4)(sp)
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STR a0, REGOFF(3)(sp)
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STR ra, REGOFF(2)(sp)
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csrr t0, mstatus
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STR t0, REGOFF(1)(sp)
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csrr a0, mcause
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csrr a1, mepc
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STR a1, REGOFF(0)(sp)
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mv a2, sp
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jal riscv_exception_handler
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/* put everything back */
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LDR t0, REGOFF(0)(sp)
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csrw mepc, t0
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LDR t0, REGOFF(1)(sp)
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csrw mstatus, t0
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LDR ra, REGOFF(2)(sp)
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LDR a0, REGOFF(3)(sp)
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LDR a1, REGOFF(4)(sp)
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LDR a2, REGOFF(5)(sp)
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LDR a3, REGOFF(6)(sp)
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LDR a4, REGOFF(7)(sp)
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LDR a5, REGOFF(8)(sp)
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LDR a6, REGOFF(9)(sp)
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LDR a7, REGOFF(10)(sp)
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LDR t0, REGOFF(11)(sp)
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LDR t1, REGOFF(12)(sp)
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LDR t2, REGOFF(13)(sp)
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LDR t3, REGOFF(14)(sp)
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LDR t4, REGOFF(15)(sp)
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LDR t5, REGOFF(16)(sp)
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LDR t6, REGOFF(17)(sp)
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addi sp, sp, REGOFF(20)
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mret
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