222 lines
5.4 KiB
ArmAsm
222 lines
5.4 KiB
ArmAsm
/*
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* Copyright (c) 2009 Corey Tabaka
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* Copyright (c) 2015 Intel Corporation
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* Copyright (c) 2016 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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#include <arch/x86/descriptor.h>
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#include <arch/x86/mmu.h>
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/* The magic number for the Multiboot header. */
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#define MULTIBOOT_HEADER_MAGIC 0x1BADB002
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/* The flags for the Multiboot header. */
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#if defined(__ELF__) && 0
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#define MULTIBOOT_HEADER_FLAGS 0x00000002
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#else
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#define MULTIBOOT_HEADER_FLAGS 0x00010002
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#endif
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/* The magic number passed by a Multiboot-compliant boot loader. */
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#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002
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#define MSR_EFER 0xc0000080
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#define EFER_LME 0x00000100
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#define PHYS_LOAD_ADDRESS (MEMBASE + KERNEL_LOAD_OFFSET)
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#define PHYS_ADDR_DELTA (KERNEL_BASE + KERNEL_LOAD_OFFSET - PHYS_LOAD_ADDRESS)
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#define PHYS(x) ((x) - PHYS_ADDR_DELTA)
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.section ".text.boot"
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.code32
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.global _start
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_start:
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jmp real_start
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.align 8
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.type multiboot_header,STT_OBJECT
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multiboot_header:
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/* magic */
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.int MULTIBOOT_HEADER_MAGIC
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/* flags */
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.int MULTIBOOT_HEADER_FLAGS
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/* checksum */
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.int -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
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#if !defined(__ELF__) || 1
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/* header_addr */
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.int PHYS(multiboot_header)
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/* load_addr */
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.int PHYS(_start)
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/* load_end_addr */
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.int PHYS(__data_end)
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/* bss_end_addr */
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.int PHYS(__bss_end)
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/* entry_addr */
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.int PHYS(real_start)
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#endif
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real_start:
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cmpl $MULTIBOOT_BOOTLOADER_MAGIC, %eax
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jne 0f
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movl %ebx, PHYS(_multiboot_info)
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0:
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/* load our new gdt by physical pointer */
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lgdt PHYS(_gdtr_phys)
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/* load our data selectors */
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movw $DATA_SELECTOR, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %fs
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movw %ax, %ss
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movw %ax, %gs
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movw %ax, %ss
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/* load initial stack pointer */
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movl $PHYS(_kstack + 4096), %esp
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/* We need to jump to our sane 32 bit CS */
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pushl $CODE_SELECTOR
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pushl $PHYS(.Lfarjump)
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retf
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.Lfarjump:
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/* zero the bss section */
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bss_setup:
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movl $PHYS(__bss_start), %edi /* starting address of the bss */
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movl $PHYS(__bss_end), %ecx /* find the length of the bss in bytes */
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subl %edi, %ecx
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shrl $2, %ecx /* convert to 32 bit words, since the bss is aligned anyway */
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2:
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movl $0, (%edi)
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addl $4, %edi
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loop 2b
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paging_setup:
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/* Preparing 64 bit paging, we will use 2MB pages covering 1GB
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for initial bootstrap, this page table will be 1 to 1 */
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/* PAE bit must be enabled for 64 bit paging*/
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mov %cr4, %eax
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btsl $(5), %eax
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mov %eax, %cr4
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/* load the physical pointer to the top level page table */
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movl $PHYS(kernel_pml4), %eax
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mov %eax, %cr3
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/* Long Mode Enabled at this point*/
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movl $MSR_EFER ,%ecx
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rdmsr
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orl $EFER_LME,%eax
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wrmsr
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/* Setting the First PML4E with a PDP table reference*/
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movl $PHYS(kernel_pdp), %eax
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orl $X86_KERNEL_PD_FLAGS, %eax
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movl %eax, PHYS(kernel_pml4)
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/* Setting the First PDPTE with a Page table reference*/
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movl $PHYS(kernel_pte), %eax
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orl $X86_KERNEL_PD_FLAGS, %eax
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movl %eax, PHYS(kernel_pdp)
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/* point the pml4e at the second high PDP (for -2GB mapping) */
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movl $PHYS(kernel_pdp_high), %eax
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orl $X86_KERNEL_PD_FLAGS, %eax
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movl %eax, PHYS(kernel_pml4 + 8*511)
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/* point the second pdp at the same low level page table */
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movl $PHYS(kernel_pte), %eax
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orl $X86_KERNEL_PD_FLAGS, %eax
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movl %eax, PHYS(kernel_pdp_high + 8*510)
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/* map the first 1GB in this table */
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movl $PHYS(kernel_pte), %esi
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movl $0x200, %ecx
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xor %eax, %eax
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0:
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mov %eax, %ebx
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shll $21, %ebx
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orl $X86_KERNEL_PD_LP_FLAGS, %ebx
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movl %ebx, (%esi)
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addl $8,%esi
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inc %eax
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loop 0b
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/* set up a linear map of the first 64GB at 0xffffff8000000000 */
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movl $PHYS(kernel_linear_map_pdp), %esi
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movl $32768, %ecx
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xor %eax, %eax
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/* loop across these page tables, incrementing the address by 2MB */
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0:
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mov %eax, %ebx
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shll $21, %ebx
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orl $X86_KERNEL_PD_LP_FLAGS, %ebx # lower word of the entry
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movl %ebx, (%esi)
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mov %eax, %ebx
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shrl $11, %ebx # upper word of the entry
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movl %ebx, 4(%esi)
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addl $8,%esi
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inc %eax
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loop 0b
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/* point the high pdp at our linear mapping page tables */
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movl $PHYS(kernel_pdp_high), %esi
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movl $64, %ecx
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movl $PHYS(kernel_linear_map_pdp), %eax
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orl $X86_KERNEL_PD_FLAGS, %eax
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0:
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movl %eax, (%esi)
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add $8, %esi
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addl $4096, %eax
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loop 0b
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/* Enabling Paging and from this point we are in
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32 bit compatibility mode*/
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mov %cr0, %eax
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btsl $(31), %eax
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mov %eax, %cr0
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/* Using another long jump to be on 64 bit mode
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after this we will be on real 64 bit mode */
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pushl $CODE_64_SELECTOR /*Need to put it in a the right CS*/
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pushl $PHYS(farjump64)
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retf
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.align 8
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.code64
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farjump64:
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/* branch to our high address */
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mov $highaddr, %rax
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jmp *%rax
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highaddr:
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/* load the high kernel stack */
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mov $(_kstack + 4096), %rsp
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/* reload the gdtr */
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lgdt _gdtr
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/* set up the idt */
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call setup_idt
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/* call the main module */
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call lk_main
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0: /* just sit around waiting for interrupts */
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hlt /* interrupts will unhalt the processor */
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pause
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jmp 0b /* so jump back to halt to conserve power */
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