106 lines
2.5 KiB
ArmAsm
106 lines
2.5 KiB
ArmAsm
/*
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* Copyright (c) 2014-2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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#include <platform/zynq.h>
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/* code run at the very beginning of the system, attempting to trap the 2nd cpu */
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FUNCTION(platform_reset)
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/* figure out our cpu number */
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mrc p15, 0, r12, c0, c0, 5 /* MPIDR */
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/* mask off the bottom 8 bits to test cpu number */
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ubfx r12, r12, #0, #8
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/* if we're the 0th cpu, continue to arm_reset */
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teq r12, #0
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beq arm_reset
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/* bump the cpu counter */
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adr r12, __cpu_trapped
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mov r11, #1
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str r11, [r12]
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dsb
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#if !WITH_SMP
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0:
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/* stay trapped here forever */
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wfe
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b 0b
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#else
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/* pass on through the reset vector, where the arm arch code will trap the cpu */
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b arm_reset
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#endif
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DATA(__cpu_trapped)
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.word 0
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#if 0
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/* disabled for now */
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/* this code attempts to remap sram to 0xfffc0000 - 0xffffffff and
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branch the cpu into the equivalent spot. Assumes the cpu is running
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at the initial 0 based mapping */
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/* a spot of the top bank of OCM memory for us to run our code from
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needs to be below where the second cpu is running (0xffffe00-0xfffffff0) */
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#define TARGET_SPOT 0xfffff800
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/* first piece of code run out of the reset vector. use
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to relocate sram to the final location at 0xfffc0000
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and switch to there */
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FUNCTION(platform_reset)
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/* relocate the below code to TARGET_SPOT */
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ldr r8, =TARGET_SPOT
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adr r9, .Lcore_reloc_start
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adr r10, .Lcore_reloc_end
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0:
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ldr r12, [r9], #4
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str r12, [r8], #4
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cmp r9, r10
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bne 0b
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/* load constants we will need below */
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ldr r8, =SLCR_BASE
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ldr r9, =SCU_CONTROL_BASE
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/* calculate the new return address this code will need to branch to */
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adr r12, .Ldone
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add r12, #0xfffc0000
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ldr r10, =TARGET_SPOT
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bx r10
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.Ldone:
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b arm_reset
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.Lcore_reloc_start:
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# use SCLR to map the sram blocks to the top of their segment
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movw r10, #SLCR_UNLOCK_KEY
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str r10, [r8, #SLCR_UNLOCK]
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ldr r10, [r8, #OCM_CFG]
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orr r10, #0xf
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str r10, [r8, #OCM_CFG]
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movw r10, #SLCR_LOCK_KEY
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str r10, [r8, #SLCR_LOCK]
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# tell the SCU to not filter first 1MB
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mov r10, #0
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str r10, [r9, #0x40] /* SCU filter start address */
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dmb
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bx r12
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.Lcore_reloc_end:
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.ltorg
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#endif
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