f0fad1590b
-move the per-cpu initialization of the gic and cortex-a9 timer into an init hook. This removes the hard coded call in arm/arch.c -make sure the timer initialization happens in the pre-threading callback, in case a secondary init hook needs the timer.
395 lines
10 KiB
C
395 lines
10 KiB
C
/*
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* Copyright (c) 2008-2014 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <debug.h>
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#include <trace.h>
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#include <stdlib.h>
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#include <err.h>
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#include <trace.h>
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#include <stdio.h>
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#include <reg.h>
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#include <arch.h>
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#include <arch/ops.h>
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#include <arch/mmu.h>
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#include <arch/arm.h>
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#include <arch/arm/mmu.h>
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#include <arch/mp.h>
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#include <kernel/spinlock.h>
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#include <kernel/thread.h>
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#include <lk/main.h>
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#include <lk/init.h>
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#include <platform.h>
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#include <target.h>
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#include <kernel/thread.h>
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#define LOCAL_TRACE 0
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#if WITH_DEV_TIMER_ARM_CORTEX_A9
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#include <dev/timer/arm_cortex_a9.h>
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#endif
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#if WITH_DEV_INTERRUPT_ARM_GIC
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#include <dev/interrupt/arm_gic.h>
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#endif
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#if WITH_DEV_CACHE_PL310
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#include <dev/cache/pl310.h>
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#endif
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/* initial and abort stacks */
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uint8_t abort_stack[ARCH_DEFAULT_STACK_SIZE * SMP_MAX_CPUS] __CPU_ALIGN;
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static void arm_basic_setup(void);
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static void spinlock_test(void);
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static void spinlock_test_secondary(void);
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#if WITH_SMP
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/* smp boot lock */
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spin_lock_t arm_boot_cpu_lock = 1;
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volatile int secondaries_to_init = 0;
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#endif
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void arch_early_init(void)
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{
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/* turn off the cache */
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arch_disable_cache(UCACHE);
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#if WITH_DEV_CACHE_PL310
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pl310_set_enable(false);
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#endif
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arm_basic_setup();
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#if WITH_SMP && ARM_CPU_CORTEX_A9
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/* enable snoop control */
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addr_t scu_base = arm_read_cbar();
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*REG32(scu_base) |= (1<<0); /* enable SCU */
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#endif
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#if ARM_WITH_MMU
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arm_mmu_early_init();
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platform_init_mmu_mappings();
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#endif
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/* turn the cache back on */
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#if WITH_DEV_CACHE_PL310
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pl310_set_enable(true);
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#endif
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arch_enable_cache(UCACHE);
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}
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void arch_init(void)
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{
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#if WITH_SMP
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arch_mp_init_percpu();
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TRACEF("midr 0x%x\n", arm_read_midr());
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TRACEF("sctlr 0x%x\n", arm_read_sctlr());
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TRACEF("actlr 0x%x\n", arm_read_actlr());
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#if ARM_CPU_CORTEX_A9
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TRACEF("cbar 0x%x\n", arm_read_cbar());
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#endif
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TRACEF("mpidr 0x%x\n", arm_read_mpidr());
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TRACEF("ttbcr 0x%x\n", arm_read_ttbcr());
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TRACEF("ttbr0 0x%x\n", arm_read_ttbr0());
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TRACEF("dacr 0x%x\n", arm_read_dacr());
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#if ARM_CPU_CORTEX_A7
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TRACEF("l2ctlr 0x%x\n", arm_read_l2ctlr());
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TRACEF("l2ectlr 0x%x\n", arm_read_l2ectlr());
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#endif
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#if ARM_CPU_CORTEX_A9
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addr_t scu_base = arm_read_cbar();
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TRACEF("SCU CONTROL 0x%x\n", *REG32(scu_base));
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uint32_t scu_config = *REG32(scu_base + 4);
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TRACEF("SCU CONFIG 0x%x\n", scu_config);
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secondaries_to_init = scu_config & 0x3;
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#elif ARM_CPU_CORTEX_A7
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uint32_t l2ctlr = arm_read_l2ctlr();
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secondaries_to_init = (l2ctlr >> 24);
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#else
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secondaries_to_init = SMP_MAX_CPUS - 1; /* TODO: get count from somewhere else, or add cpus as they boot */
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#endif
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lk_init_secondary_cpus(secondaries_to_init);
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TRACEF("releasing %d secondary cpus\n", secondaries_to_init);
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/* release the secondary cpus */
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spin_unlock(&arm_boot_cpu_lock);
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/* flush the release of the lock, since the secondary cpus are running without cache on */
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arch_clean_cache_range((addr_t)&arm_boot_cpu_lock, sizeof(arm_boot_cpu_lock));
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/* wait for all of the secondary cpus to boot */
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while (secondaries_to_init > 0) {
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__asm__ volatile("wfe");
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}
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#endif
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//spinlock_test();
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/* finish intializing the mmu */
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arm_mmu_init();
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}
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#if WITH_SMP
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void arm_secondary_entry(void)
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{
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arm_basic_setup();
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/* enable the local L1 cache */
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//arch_enable_cache(UCACHE);
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// XXX may not be safe, but just hard enable i and d cache here
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// at the moment cannot rely on arch_enable_cache not dumping the L2
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uint32_t sctlr = arm_read_sctlr();
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sctlr |= (1<<12) | (1<<2); // enable i and dcache
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arm_write_sctlr(sctlr);
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/* run early secondary cpu init routines up to the threading level */
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lk_init_level(LK_INIT_FLAG_SECONDARY_CPUS, LK_INIT_LEVEL_EARLIEST, LK_INIT_LEVEL_THREADING - 1);
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arch_mp_init_percpu();
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TRACEF("cpu num %d\n", arch_curr_cpu_num());
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TRACEF("sctlr 0x%x\n", arm_read_sctlr());
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TRACEF("actlr 0x%x\n", arm_read_actlr());
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#if ARM_CPU_CORTEX_A9
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addr_t scu_base = arm_read_cbar();
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TRACEF("SCU CONTROL 0x%x\n", *REG32(scu_base));
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TRACEF("SCU CONFIG 0x%x\n", *REG32(scu_base + 4));
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#endif
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/* we're done, tell the main cpu we're up */
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atomic_add(&secondaries_to_init, -1);
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__asm__ volatile("sev");
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lk_secondary_cpu_entry();
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}
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#endif
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static void arm_basic_setup(void)
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{
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uint32_t sctlr = arm_read_sctlr();
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/* ARMV7 bits */
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sctlr &= ~(1<<10); /* swp disable */
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sctlr |= (1<<11); /* enable program flow prediction */
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sctlr &= ~(1<<14); /* random cache/tlb replacement */
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sctlr &= ~(1<<25); /* E bit set to 0 on exception */
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sctlr &= ~(1<<30); /* no thumb exceptions */
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arm_write_sctlr(sctlr);
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uint32_t actlr = arm_read_actlr();
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#if ARM_CPU_CORTEX_A9
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actlr |= (1<<2); /* enable dcache prefetch */
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#if WITH_DEV_CACHE_PL310
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actlr |= (1<<7); /* L2 exclusive cache */
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actlr |= (1<<3); /* L2 write full line of zeroes */
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actlr |= (1<<1); /* L2 prefetch hint enable */
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#endif
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#if WITH_SMP
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/* enable smp mode, cache and tlb broadcast */
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actlr |= (1<<6) | (1<<0);
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#endif
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#endif // ARM_CPU_CORTEX_A9
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#if ARM_CPU_CORTEX_A7
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#if WITH_SMP
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/* enable smp mode */
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actlr |= (1<<6);
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#endif
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#endif // ARM_CPU_CORTEX_A7
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arm_write_actlr(actlr);
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#if ENABLE_CYCLE_COUNTER && ARM_ISA_ARMV7
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/* enable the cycle count register */
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uint32_t en;
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__asm__ volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (en));
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en &= ~(1<<3); /* cycle count every cycle */
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en |= 1; /* enable all performance counters */
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__asm__ volatile("mcr p15, 0, %0, c9, c12, 0" :: "r" (en));
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/* enable cycle counter */
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en = (1<<31);
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__asm__ volatile("mcr p15, 0, %0, c9, c12, 1" :: "r" (en));
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#endif
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#if ARM_WITH_VFP
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/* enable cp10 and cp11 */
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uint32_t val = arm_read_cpacr();
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val |= (3<<22)|(3<<20);
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arm_write_cpacr(val);
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/* set enable bit in fpexc */
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__asm__ volatile("mrc p10, 7, %0, c8, c0, 0" : "=r" (val));
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val |= (1<<30);
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__asm__ volatile("mcr p10, 7, %0, c8, c0, 0" :: "r" (val));
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/* make sure the fpu starts off disabled */
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arm_fpu_set_enable(false);
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#endif
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/* set the vector base to our exception vectors so we dont need to double map at 0 */
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#if ARM_ISA_ARMV7
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arm_write_vbar(KERNEL_BASE + KERNEL_LOAD_OFFSET);
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#endif
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}
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void arch_quiesce(void)
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{
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#if ENABLE_CYCLE_COUNTER
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#if ARM_ISA_ARMV7
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/* disable the cycle count and performance counters */
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uint32_t en;
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__asm__ volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (en));
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en &= ~1; /* disable all performance counters */
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__asm__ volatile("mcr p15, 0, %0, c9, c12, 0" :: "r" (en));
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/* disable cycle counter */
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en = 0;
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__asm__ volatile("mcr p15, 0, %0, c9, c12, 1" :: "r" (en));
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#endif
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#if ARM_CPU_ARM1136
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/* disable the cycle count and performance counters */
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uint32_t en;
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__asm__ volatile("mrc p15, 0, %0, c15, c12, 0" : "=r" (en));
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en &= ~1; /* disable all performance counters */
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__asm__ volatile("mcr p15, 0, %0, c15, c12, 0" :: "r" (en));
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#endif
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#endif
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}
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#if ARM_ISA_ARMV7
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/* virtual to physical translation */
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status_t arm_vtop(addr_t va, addr_t *pa)
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{
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arm_write_ats1cpr(va & ~(PAGE_SIZE-1));
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uint32_t par = arm_read_par();
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if (par & 1)
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return ERR_NOT_FOUND;
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if (pa) {
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*pa = (par & 0xfffff000) | (va & 0xfff);
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}
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return NO_ERROR;
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}
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#endif
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void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3)
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{
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LTRACEF("entry %p, args 0x%lx 0x%lx 0x%lx 0x%lx\n", entry, arg0, arg1, arg2, arg3);
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/* we are going to shut down the system, start by disabling interrupts */
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arch_disable_ints();
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/* give target and platform a chance to put hardware into a suitable
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* state for chain loading.
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*/
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target_quiesce();
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platform_quiesce();
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arch_quiesce();
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#if WITH_KERNEL_VM
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/* get the physical address of the entry point we're going to branch to */
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paddr_t entry_pa;
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if (arm_vtop((addr_t)entry, &entry_pa) < 0) {
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panic("error translating entry physical address\n");
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}
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/* add the low bits of the virtual address back */
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entry_pa |= ((addr_t)entry & 0xfff);
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LTRACEF("entry pa 0x%lx\n", entry_pa);
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/* figure out the mapping for the chain load routine */
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paddr_t loader_pa;
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if (arm_vtop((addr_t)&arm_chain_load, &loader_pa) < 0) {
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panic("error translating loader physical address\n");
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}
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/* add the low bits of the virtual address back */
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loader_pa |= ((addr_t)&arm_chain_load & 0xfff);
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paddr_t loader_pa_section = ROUNDDOWN(loader_pa, SECTION_SIZE);
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LTRACEF("loader address %p, phys 0x%lx, surrounding large page 0x%lx\n",
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&arm_chain_load, loader_pa, loader_pa_section);
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/* using large pages, map around the target location */
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arch_mmu_map(loader_pa_section, loader_pa_section, (2 * SECTION_SIZE / PAGE_SIZE), 0);
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LTRACEF("disabling instruction/data cache\n");
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arch_disable_cache(UCACHE);
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#if WITH_DEV_CACHE_PL310
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pl310_set_enable(false);
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#endif
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LTRACEF("branching to physical address of loader\n");
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/* branch to the physical address version of the chain loader routine */
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void (*loader)(paddr_t entry, ulong, ulong, ulong, ulong) __NO_RETURN = (void *)loader_pa;
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loader(entry_pa, arg0, arg1, arg2, arg3);
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#else
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#error handle the non vm path (should be simpler)
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#endif
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}
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static spin_lock_t lock = 0;
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static void spinlock_test(void)
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{
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TRACE_ENTRY;
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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TRACEF("cpu0: i have the lock\n");
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spin(1000000);
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TRACEF("cpu0: releasing it\n");
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spin_unlock_irqrestore(&lock, state);
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spin(1000000);
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}
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static void spinlock_test_secondary(void)
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{
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TRACE_ENTRY;
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spin(500000);
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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TRACEF("cpu1: i have the lock\n");
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spin(250000);
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TRACEF("cpu1: releasing it\n");
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spin_unlock_irqrestore(&lock, state);
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}
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/* vim: set ts=4 sw=4 noexpandtab: */
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