Files
lk/project/qemu-riscv32-test.mk
Travis Geiselbrecht 8cf28bbdcf [arch][riscv] Initial port to a riscv32 sifive target
Currently targets qemu's sifive_e machine, which is a split flash/ram
machine, much like the Sifive HiFive1. Untested as of yet on a real
HiFive1.

Basic support including interrupts and architectural timers in place.
2018-12-16 16:44:23 -08:00

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Makefile

include project/target/qemu-riscv32.mk
include project/virtual/test.mk