180 lines
6.0 KiB
C
180 lines
6.0 KiB
C
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <err.h>
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#include <debug.h>
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#include <dev/uart.h>
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#include <platform.h>
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#include <platform/stm32.h>
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#include <arch/arm/cm.h>
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uint32_t SystemCoreClock = HSI_VALUE;
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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__HAL_RCC_PWR_CLK_ENABLE();
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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}
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/**
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* @brief System Clock Configuration
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* The system Clock is configured as follow :
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* System Clock source = PLL (HSE or HSI)
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* SYSCLK(Hz) = 216000000
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* HCLK(Hz) = 216000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 4
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* APB2 Prescaler = 2
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* HSE Frequency(Hz) = 25000000
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* PLL_M = 25 or 16
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* PLL_N = 432
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* PLL_P = 2
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* PLL_Q = 9
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* VDD(V) = 3.3
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* Main regulator output voltage = Scale1 mode
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* Flash Latency(WS) = 7
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* @param None
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* @retval None
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*/
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static void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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HAL_StatusTypeDef ret = HAL_OK;
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#if defined(USE_HSE_XTAL)
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/* Enable HSE Oscillator and activate PLL with HSE as source.
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* The external XTAL is a more stable clock source.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 25;
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RCC_OscInitStruct.PLL.PLLN = 432;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 9;
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#else
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/* Enable HSI Oscillator and activate PLL with HSI as source.
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* Some boards like STm32756G-EVAL2 seem to malfuction with the
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* HSE xtal configuration.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = 16;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 16;
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RCC_OscInitStruct.PLL.PLLN = 432;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 9;
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#endif
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ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
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if (ret != HAL_OK) {
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while (1) { ; }
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}
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/* Activate the OverDrive to reach the 216 MHz Frequency */
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ret = HAL_PWREx_EnableOverDrive();
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if (ret != HAL_OK) {
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while (1) { ; }
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}
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
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if (ret != HAL_OK) {
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while (1) { ; }
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}
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}
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void platform_early_init(void)
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{
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// Do general system init
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SystemInit();
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SystemClock_Config();
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// Enable the flash ART controller
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__HAL_FLASH_ART_ENABLE();
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__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
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// Start the systick timer
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uint32_t sysclk = HAL_RCC_GetSysClockFreq();
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arm_cm_systick_init(sysclk);
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stm32_timer_early_init();
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stm32_gpio_early_init();
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stm32_flash_early_init();
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/* clear the reboot reason */
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RCC->CSR |= (1<<24);
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// ITM_SendChar('1');
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}
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void platform_init(void)
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{
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printf("clocks:\n");
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printf("\tsysclk %u\n", HAL_RCC_GetSysClockFreq());
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printf("\thclk %u\n", HAL_RCC_GetHCLKFreq());
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printf("\tpclk1 %u\n", HAL_RCC_GetPCLK1Freq());
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printf("\tpclk2 %u\n", HAL_RCC_GetPCLK2Freq());
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stm32_timer_init();
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stm32_flash_init();
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// ITM_SendChar('2');
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}
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