125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
/*
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* Copyright (c) 2014 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <debug.h>
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#include <arch.h>
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#include <arch/ops.h>
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#include <arch/arm64.h>
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#include <arch/arm64/mmu.h>
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#include <arch/mp.h>
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#include <kernel/thread.h>
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#include <lk/init.h>
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#include <lk/main.h>
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#include <platform.h>
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#include <trace.h>
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#define LOCAL_TRACE 0
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#if WITH_SMP
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/* smp boot lock */
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static spin_lock_t arm_boot_cpu_lock = 1;
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static volatile int secondaries_to_init = 0;
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#endif
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static void arm64_cpu_early_init(void)
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{
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/* set the vector base */
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ARM64_WRITE_SYSREG(VBAR_EL1, (uint64_t)&arm64_exception_base);
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/* switch to EL1 */
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unsigned int current_el = ARM64_READ_SYSREG(CURRENTEL) >> 2;
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if (current_el > 1) {
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arm64_el3_to_el1();
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}
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arch_enable_fiqs();
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}
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void arch_early_init(void)
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{
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arm64_cpu_early_init();
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platform_init_mmu_mappings();
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}
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void arch_init(void)
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{
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#if WITH_SMP
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arch_mp_init_percpu();
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LTRACEF("midr_el1 0x%llx\n", ARM64_READ_SYSREG(midr_el1));
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secondaries_to_init = SMP_MAX_CPUS - 1; /* TODO: get count from somewhere else, or add cpus as they boot */
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lk_init_secondary_cpus(secondaries_to_init);
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LTRACEF("releasing %d secondary cpus\n", secondaries_to_init);
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/* release the secondary cpus */
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spin_unlock(&arm_boot_cpu_lock);
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/* flush the release of the lock, since the secondary cpus are running without cache on */
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arch_clean_cache_range((addr_t)&arm_boot_cpu_lock, sizeof(arm_boot_cpu_lock));
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#endif
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}
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void arch_quiesce(void)
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{
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}
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void arch_idle(void)
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{
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__asm__ volatile("wfi");
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}
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void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3)
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{
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PANIC_UNIMPLEMENTED;
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}
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#if WITH_SMP
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void arm64_secondary_entry(ulong asm_cpu_num)
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{
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uint cpu = arch_curr_cpu_num();
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if (cpu != asm_cpu_num)
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return;
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arm64_cpu_early_init();
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spin_lock(&arm_boot_cpu_lock);
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spin_unlock(&arm_boot_cpu_lock);
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/* run early secondary cpu init routines up to the threading level */
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lk_init_level(LK_INIT_FLAG_SECONDARY_CPUS, LK_INIT_LEVEL_EARLIEST, LK_INIT_LEVEL_THREADING - 1);
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arch_mp_init_percpu();
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LTRACEF("cpu num %d\n", cpu);
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/* we're done, tell the main cpu we're up */
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atomic_add(&secondaries_to_init, -1);
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__asm__ volatile("sev");
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lk_secondary_cpu_entry();
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}
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#endif
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