e50d7db612
Add support for running LK in supervisor mode or machine mode. - Macro-ify CSR access to use correct CSR # or use SBI call as req'd - Add support to make SBI calls - Split CLINT and lk timer abstraction so that RISC-V timer can use SBI as required. - Add support for booting other harts as primary since hart0 on U540 does not support S-mode. A map is used to get LK cpu number from hartid.
73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
/*
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* Copyright (c) 2018 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/reg.h>
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#include <lk/debug.h>
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#include <lk/trace.h>
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#include <lk/err.h>
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#include <lk/trace.h>
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#include <arch/riscv.h>
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#include <arch/ops.h>
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#include <platform.h>
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#include <platform/timer.h>
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#define LOCAL_TRACE 0
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static platform_timer_callback timer_cb;
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static void *timer_arg;
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status_t platform_set_oneshot_timer (platform_timer_callback callback, void *arg, lk_time_t interval) {
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LTRACEF("cb %p, arg %p, interval %u\n", callback, arg, interval);
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// disable timer
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riscv_csr_clear(RISCV_CSR_XIE, RISCV_CSR_XIE_TIE);
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timer_cb = callback;
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timer_arg = arg;
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// enable the timer
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riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_TIE);
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// convert interval to ticks
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uint64_t ticks = riscv_get_time() + ((interval * ARCH_RISCV_MTIME_RATE) / 1000u);
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#if RISCV_M_MODE
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extern void clint_set_timer(uint64_t ticks);
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clint_set_timer(ticks);
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#elif RISCV_S_MODE
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sbi_set_timer(ticks);
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#endif
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return NO_ERROR;
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}
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lk_bigtime_t current_time_hires(void) {
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return riscv_get_time() / (ARCH_RISCV_MTIME_RATE / 1000000u);
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}
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lk_time_t current_time(void) {
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return riscv_get_time() / (ARCH_RISCV_MTIME_RATE / 1000u);
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}
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void platform_stop_timer(void) {
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riscv_csr_clear(RISCV_CSR_XIE, RISCV_CSR_XIE_TIE);
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}
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enum handler_return riscv_timer_exception(void) {
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LTRACEF("tick\n");
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riscv_csr_clear(RISCV_CSR_XIE, RISCV_CSR_XIE_TIE);
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enum handler_return ret = INT_NO_RESCHEDULE;
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if (timer_cb) {
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ret = timer_cb(timer_arg, current_time());
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}
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return ret;
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} |