e50d7db612
Add support for running LK in supervisor mode or machine mode. - Macro-ify CSR access to use correct CSR # or use SBI call as req'd - Add support to make SBI calls - Split CLINT and lk timer abstraction so that RISC-V timer can use SBI as required. - Add support for booting other harts as primary since hart0 on U540 does not support S-mode. A map is used to get LK cpu number from hartid.
67 lines
1.5 KiB
C
67 lines
1.5 KiB
C
/*
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* Copyright (c) 2019 Elliot Berman
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#include <config.h>
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#include <lk/reg.h>
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#include <arch/arch_ops.h>
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#if RISCV_M_MODE
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// platform must define these
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#ifndef ARCH_RISCV_CLINT_BASE
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#error Platform must define ARCH_RISCV_CLINT_BASE
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#endif
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#ifndef ARCH_RISCV_MTIME_RATE
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#error Platform must define ARCH_RISCV_MTIME_RATE
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#endif
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#define CLINT_MSIP(h) (ARCH_RISCV_CLINT_BASE + (4 * (h)))
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#define CLINT_MTIMECMP(h) (ARCH_RISCV_CLINT_BASE + 0x4000 + (8 * (h)))
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#define CLINT_MTIME (ARCH_RISCV_CLINT_BASE + 0xbff8)
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static inline void clint_ipi_send(unsigned long target_hart) {
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if (target_hart >= SMP_MAX_CPUS)
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return;
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*REG32(CLINT_MSIP(target_hart)) = 1;
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}
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static inline void clint_ipi_clear(unsigned long target_hart) {
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if (target_hart >= SMP_MAX_CPUS)
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return;
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*REG32(CLINT_MSIP(target_hart)) = 0;
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}
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static inline void clint_set_timer(uint64_t ticks) {
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*REG64(CLINT_MTIMECMP(riscv_current_hart())) = ticks;
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}
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static inline uint64_t riscv_get_time(void) {
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return *REG64(CLINT_MTIME);
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}
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static inline void clint_send_ipis(const unsigned long *hart_mask) {
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unsigned long cur_hart = riscv_current_hart(), h, m = *hart_mask;
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for (h = 0; h < SMP_MAX_CPUS && m; h++, m >>= 1) {
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if ((m & 1) && (h != cur_hart)) {
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clint_ipi_send(h);
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}
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}
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if(*hart_mask & (1 << riscv_current_hart())) {
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clint_ipi_send(cur_hart);
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}
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}
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#endif
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