58 lines
1.8 KiB
C
58 lines
1.8 KiB
C
/*
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* Copyright (c) 2019 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <assert.h>
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#include <lk/trace.h>
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#include <lk/debug.h>
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#include <stdint.h>
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#include <arch/ops.h>
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#include <arch/vax.h>
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#define LOCAL_TRACE 0
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extern uint8_t irq_stack[1024];
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void arch_early_init(void) {
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// set the top level exception handler
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//riscv_csr_write(mtvec, (uintptr_t)&riscv_exception_entry);
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// mask all exceptions, just in case
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//riscv_csr_clear(mstatus, RISCV_STATUS_MIE);
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//riscv_csr_clear(mie, RISCV_MIE_MTIE | RISCV_MIE_MSIE | RISCV_MIE_SEIE | RISCV_MIE_MEIE);
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// enable cycle counter (disabled for now, unimplemented on sifive-e)
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//riscv_csr_set(mcounteren, 1);
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}
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void arch_init(void) {
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// print some arch info
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//dprintf(INFO, "RISCV: mvendorid %#lx marchid %#lx mimpid %#lx mhartid %#lx\n",
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// riscv_csr_read(mvendorid), riscv_csr_read(marchid),
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// riscv_csr_read(mimpid), riscv_csr_read(mhartid));
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//dprintf(INFO, "RISCV: misa %#lx\n", riscv_csr_read(misa));
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// enable external interrupts
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//riscv_csr_set(mie, RISCV_MIE_MEIE);
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}
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void arch_idle(void) {
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// __asm__ volatile("wfi");
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}
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void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) {
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PANIC_UNIMPLEMENTED;
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}
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/* unimplemented cache operations */
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void arch_disable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_enable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_clean_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_clean_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_sync_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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