6b89609887
Rearrange some of the cpu initialization code to be runnable on each cpu as they come up. Complete the 64bit bootstrap mechanism and call into C code. Makes it as far as trying to reschedule via an IPI. Need to implement local apic based IPI mechanism.
151 lines
4.0 KiB
C
151 lines
4.0 KiB
C
/*
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* Copyright (c) 2009 Corey Tabaka
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* Copyright (c) 2015 Intel Corporation
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/debug.h>
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#include <arch.h>
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#include <arch/ops.h>
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#include <arch/x86.h>
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#include <arch/x86/mmu.h>
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#include <arch/x86/descriptor.h>
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#include <arch/x86/feature.h>
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#include <arch/fpu.h>
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#include <arch/mmu.h>
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#include <kernel/vm.h>
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#include <platform.h>
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#include <sys/types.h>
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/* Describe how start.S sets up the MMU.
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* These data structures are later used by vm routines to lookup pointers
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* to physical pages based on physical addresses.
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*/
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struct mmu_initial_mapping mmu_initial_mappings[] = {
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/* 64GB of the first 64GB of memory mapped 1:1 */
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{
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.phys = MEMBASE,
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.virt = KERNEL_ASPACE_BASE,
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.size = PHYSMAP_SIZE, /* x86-64 maps first 64GB by default, 1GB on x86-32, 16MB in legacy mode */
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.flags = 0,
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.name = "physmap"
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},
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#if ARCH_X86_64
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/* Another linear map of the first GB of memory where the kernel image
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* lives at the top of the address space. */
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{
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.phys = MEMBASE,
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.virt = KERNEL_BASE,
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.size = 1*GB,
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.flags = 0,
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.name = "kernel"
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},
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#endif
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/* null entry to terminate the list */
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{ 0 }
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};
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/* early stack */
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uint8_t _kstack[PAGE_SIZE] __ALIGNED(sizeof(unsigned long));
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/* save a pointer to the multiboot information coming in from whoever called us */
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/* make sure it lives in .data to avoid it being wiped out by bss clearing */
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__SECTION(".data") uint32_t _multiboot_info;
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/* main tss */
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static tss_t system_tss __ALIGNED(16);
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void x86_early_init_percpu(void) {
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// enable caches
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clear_in_cr0(X86_CR0_NW | X86_CR0_CD);
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// configure the system TSS
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// XXX move to a per cpu TSS in the percpu structure
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#if ARCH_X86_32
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system_tss.esp0 = 0;
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system_tss.ss0 = DATA_SELECTOR;
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system_tss.ss1 = 0;
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system_tss.ss2 = 0;
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system_tss.eflags = 0x00003002;
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system_tss.bitmap = offsetof(tss_32_t, tss_bitmap);
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system_tss.trace = 1; // trap on hardware task switch
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#elif ARCH_X86_64
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/* nothing to be done here, a fully zeroed TSS is a good starting point */
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#endif
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const uint selector = TSS_SELECTOR_BASE + 8 * arch_curr_cpu_num();
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x86_set_gdt_descriptor(selector, &system_tss, sizeof(system_tss), 1, 0, 0, SEG_TYPE_TSS, 0, 0);
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x86_ltr(selector);
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x86_mmu_early_init_percpu();
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#if X86_WITH_FPU
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x86_fpu_early_init_percpu();
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#endif
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}
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/* early initialization of the system, on the boot cpu, usually before any sort of
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* printf output is available.
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*/
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void arch_early_init(void) {
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x86_feature_early_init();
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x86_mmu_early_init();
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#if X86_WITH_FPU
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x86_fpu_early_init();
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#endif
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x86_early_init_percpu();
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}
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/* later initialization pass, once the main kernel is initialized and scheduling has begun */
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void arch_init(void) {
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x86_feature_init();
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x86_mmu_init();
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#if X86_WITH_FPU
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x86_fpu_init();
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#endif
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}
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void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) {
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PANIC_UNIMPLEMENTED;
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}
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void arch_enter_uspace(vaddr_t entry_point, vaddr_t user_stack_top) {
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PANIC_UNIMPLEMENTED;
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#if 0
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DEBUG_ASSERT(IS_ALIGNED(user_stack_top, 16));
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thread_t *ct = get_current_thread();
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vaddr_t kernel_stack_top = (uintptr_t)ct->stack + ct->stack_size;
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kernel_stack_top = ROUNDDOWN(kernel_stack_top, 16);
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/* set up a default spsr to get into 64bit user space:
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* zeroed NZCV
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* no SS, no IL, no D
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* all interrupts enabled
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* mode 0: EL0t
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*/
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uint32_t spsr = 0;
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arch_disable_ints();
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asm volatile(
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"mov sp, %[kstack];"
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"msr sp_el0, %[ustack];"
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"msr elr_el1, %[entry];"
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"msr spsr_el1, %[spsr];"
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"eret;"
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:
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: [ustack]"r"(user_stack_top),
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[kstack]"r"(kernel_stack_top),
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[entry]"r"(entry_point),
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[spsr]"r"(spsr)
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: "memory");
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__UNREACHABLE;
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#endif
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}
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