177 lines
3.6 KiB
ArmAsm
177 lines
3.6 KiB
ArmAsm
/*
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* Copyright (c) 2009 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <asm.h>
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.text
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/* void arch_enable_ints(void); */
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FUNCTION(arch_enable_ints)
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mfsr r8, 0 /* sr */
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cbr r8, 16
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mtsr 0, r8 /* sr */
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retal r12
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/* void arch_disable_ints(void); */
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FUNCTION(arch_disable_ints)
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mfsr r8, 0 /* sr */
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sbr r8, 16
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mtsr 0, r8 /* sr */
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retal r12
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/* int atomic_swap(int *ptr, int val); */
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FUNCTION(atomic_swap)
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#if 0
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swp r2, r1, [r0]
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mov r0, r2
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bx lr
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#endif
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retal r12
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/* int atomic_add(int *ptr, int val); */
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FUNCTION(atomic_add)
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#if 0
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#if ARM_ISA_ARMV6 || ARM_ISA_ARMV7
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/* use load/store exclusive */
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.L_loop_add:
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ldrex r12, [r0]
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add r2, r12, r1
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strex r3, r2, [r0]
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cmp r3, #0
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bne .L_loop_add
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/* save old value */
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mov r0, r12
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bx lr
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#else
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/* disable interrupts, do the add, and reenable */
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mrs r2, cpsr
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mov r12, r2
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orr r2, r2, #(3<<6)
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msr cpsr_c, r2
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/* ints disabled, old cpsr state in r12 */
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/* do the add, leave the previous value in r0 */
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mov r3, r0
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ldr r0, [r3]
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add r2, r0, r1
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str r2, [r3]
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/* restore interrupts and exit */
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msr cpsr_c, r12
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bx lr
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#endif
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#endif
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retal r12
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/* int atomic_and(int *ptr, int val); */
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FUNCTION(atomic_and)
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#if 0
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#if ARM_ISA_ARMV6 || ARM_ISA_ARMV7
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/* use load/store exclusive */
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.L_loop_and:
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ldrex r12, [r0]
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and r2, r12, r1
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strex r3, r2, [r0]
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cmp r3, #0
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bne .L_loop_and
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/* save old value */
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mov r0, r12
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bx lr
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#else
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/* disable interrupts, do the and, and reenable */
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mrs r2, cpsr
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mov r12, r2
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orr r2, r2, #(3<<6)
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msr cpsr_c, r2
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/* ints disabled, old cpsr state in r12 */
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/* do the and, leave the previous value in r0 */
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mov r3, r0
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ldr r0, [r3]
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and r2, r0, r1
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str r2, [r3]
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/* restore interrupts and exit */
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msr cpsr_c, r12
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bx lr
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#endif
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#endif
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retal r12
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/* int atomic_or(int *ptr, int val); */
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FUNCTION(atomic_or)
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#if 0
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#if ARM_ISA_ARMV6 || ARM_ISA_ARMV7
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/* use load/store exclusive */
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.L_loop_or:
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ldrex r12, [r0]
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orr r2, r12, r1
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strex r3, r2, [r0]
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cmp r3, #0
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bne .L_loop_or
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/* save old value */
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mov r0, r12
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bx lr
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#else
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/* disable interrupts, do the or, and reenable */
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mrs r2, cpsr
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mov r12, r2
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orr r2, r2, #(3<<6)
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msr cpsr_c, r2
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/* ints disabled, old cpsr state in r12 */
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/* do the or, leave the previous value in r0 */
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mov r3, r0
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ldr r0, [r3]
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orr r2, r0, r1
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str r2, [r3]
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/* restore interrupts and exit */
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msr cpsr_c, r12
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bx lr
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#endif
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#endif
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retal r12
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/* void arch_idle(); */
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FUNCTION(arch_idle)
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sleep 0
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retal r12
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/* void arch_switch_stacks_and_call(addr_t call, addr_t stack) */
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FUNCTION(arch_switch_stacks_and_call)
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mov sp, r11
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icall r12
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/* uint32_t arch_cycle_count(void); */
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FUNCTION(arch_cycle_count)
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retal 0
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