+ When setting GPIOs, the MASK_DATA registers are used. Code was
properly computing which register to use based on register index
(either LSW or MSW), but was improperly computing the mask/value to
set when the GPIO to be manipulated existed in the upper 16 bits
(the shift needed to be offset by 16 bits and was not).
+ Do not manipulate things like the IO driver type, drive speed, and
so on when enabling/disabling the pullup in the SLCR registers.
Previously, whenever a GPIO was being configured, the SLCR register
was being set to be 1.8v LVCMOS, and having the DISABLE RCV bit set.
Things like the IO type have been set by the platform and should not
be manipulated by the GPIO driver. Now, the GPIO code leaves those
bits the way they were configured, and changes only the PULLUP bit
as well as the 4 levels mux bits (arguably, it should not even
change the mux bits; it is the platform's job to properly mux the
pins).
+ Address an issue with the subtle (undocumented) difference between
the DIRM and the OEN bits when configuring for input vs. output.
Please read the extensive comment in the code for details.
Change-Id: I160069eeef92b1cf0763274ccb64c5d14744f563
Signed-off-by: John Grossman <johngro@google.com>
c2b645ef8a