165f826ca3
Old PLIC_PRIORITY macro had an off-by-one bug, causing you to set the priority for the wrong IRQ.
113 lines
3.3 KiB
C
113 lines
3.3 KiB
C
/*
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* Copyright (c) 2018 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include "platform_p.h"
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#include <assert.h>
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#include <lk/err.h>
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#include <lk/debug.h>
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#include <lk/reg.h>
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#include <lk/trace.h>
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#include <kernel/debug.h>
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#include <kernel/thread.h>
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#include <platform/interrupts.h>
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#include <platform/virt.h>
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#define LOCAL_TRACE 0
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// Driver for PLIC implementation for qemu riscv virt machine
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#define PLIC_PRIORITY(irq) (PLIC_BASE_VIRT + 4 * (irq))
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#define PLIC_PENDING(irq) (PLIC_BASE_VIRT + 0x1000 + (4 * ((irq) / 32)))
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#define PLIC_ENABLE(irq, hart) (PLIC_BASE_VIRT + 0x2000 + (0x80 * PLIC_HART_IDX(hart)) + (4 * ((irq) / 32)))
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#define PLIC_THRESHOLD(hart) (PLIC_BASE_VIRT + 0x200000 + (0x1000 * PLIC_HART_IDX(hart)))
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#define PLIC_COMPLETE(hart) (PLIC_BASE_VIRT + 0x200004 + (0x1000 * PLIC_HART_IDX(hart)))
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#define PLIC_CLAIM(hart) PLIC_COMPLETE(hart)
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static struct int_handlers {
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int_handler handler;
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void *arg;
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} handlers[NUM_IRQS];
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void plic_early_init(void) {
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// mask all irqs and set their priority to 1
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// TODO: mask on all the other cpus too
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for (int i = 1; i < NUM_IRQS; i++) {
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*REG32(PLIC_ENABLE(i, riscv_current_hart())) &= ~(1 << (i % 32));
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*REG32(PLIC_PRIORITY(i)) = 1;
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}
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// set global priority threshold to 0
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*REG32(PLIC_THRESHOLD(riscv_current_hart())) = 0;
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}
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void plic_init(void) {
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}
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status_t mask_interrupt(unsigned int vector) {
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*REG32(PLIC_ENABLE(vector, riscv_current_hart())) &= ~(1 << (vector % 32));
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return NO_ERROR;
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}
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status_t unmask_interrupt(unsigned int vector) {
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*REG32(PLIC_ENABLE(vector, riscv_current_hart())) |= (1 << (vector % 32));
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return NO_ERROR;
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}
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void register_int_handler(unsigned int vector, int_handler handler, void *arg) {
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LTRACEF("vector %u handler %p arg %p\n", vector, handler, arg);
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DEBUG_ASSERT(vector < NUM_IRQS);
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handlers[vector].handler = handler;
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handlers[vector].arg = arg;
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}
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void register_int_handler_msi(unsigned int vector, int_handler handler, void *arg, bool edge) {
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PANIC_UNIMPLEMENTED;
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}
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enum handler_return riscv_platform_irq(void) {
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// see what irq triggered it
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uint32_t vector = *REG32(PLIC_CLAIM(riscv_current_hart()));
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LTRACEF("vector %u\n", vector);
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if (unlikely(vector == 0)) {
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// nothing pending
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return INT_NO_RESCHEDULE;
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}
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THREAD_STATS_INC(interrupts);
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KEVLOG_IRQ_ENTER(vector);
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enum handler_return ret = INT_NO_RESCHEDULE;
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if (handlers[vector].handler) {
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ret = handlers[vector].handler(handlers[vector].arg);
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}
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// ack the interrupt
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*REG32(PLIC_COMPLETE(riscv_current_hart())) = vector;
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KEVLOG_IRQ_EXIT(vector);
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return ret;
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}
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status_t platform_pci_int_to_vector(unsigned int pci_int, unsigned int *vector) {
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// at the moment there's no translation between PCI IRQs and native irqs
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*vector = pci_int;
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return NO_ERROR;
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}
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status_t platform_allocate_interrupts(size_t count, uint align_log2, bool msi, unsigned int *vector) {
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return ERR_NOT_SUPPORTED;
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}
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status_t platform_compute_msi_values(unsigned int vector, unsigned int cpu, bool edge,
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uint64_t *msi_address_out, uint16_t *msi_data_out) {
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return ERR_NOT_SUPPORTED;
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}
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