c66ad44efa
Still TODO: -Set the timer rate properly -Fix nonzero based hart secondary cpu boot -Try to parse the device tree for some information
42 lines
1.0 KiB
Makefile
42 lines
1.0 KiB
Makefile
LOCAL_DIR := $(GET_LOCAL_DIR)
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MODULE := $(LOCAL_DIR)
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ARCH := riscv
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SUBARCH ?= 64
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RISCV_MODE ?= supervisor
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WITH_SMP ?= true
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SMP_MAX_CPUS ?= 4
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LK_HEAP_IMPLEMENTATION ?= dlmalloc
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RISCV_FPU ?= true
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RISCV_MMU ?= sv39
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MODULE_DEPS += lib/cbuf
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MODULE_DEPS += lib/fdt
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MODULE_DEPS += lib/fdtwalk
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#MODULE_DEPS += dev/bus/pci
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#MODULE_DEPS += dev/bus/pci/drivers
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MODULE_SRCS += $(LOCAL_DIR)/platform.c
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MODULE_SRCS += $(LOCAL_DIR)/plic.c
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MODULE_SRCS += $(LOCAL_DIR)/uart.c
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MEMBASE ?= 0x40000000
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MEMSIZE ?= 0x10000000 # default to 256MB
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ifeq ($(RISCV_MODE),supervisor)
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# offset the kernel to account for OpenSBI using the bottom
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KERNEL_LOAD_OFFSET ?= 0x00200000 # kernel load offset
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endif
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# set some global defines based on capability
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GLOBAL_DEFINES += ARCH_RISCV_CLINT_BASE=0x0c000000
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GLOBAL_DEFINES += ARCH_RISCV_MTIME_RATE=10000000
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# we can revert to a poll based uart spin routine
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GLOBAL_DEFINES += PLATFORM_SUPPORTS_PANIC_SHELL=1
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# do not need to implement any cache ops
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GLOBAL_DEFINES += RISCV_NO_CACHE_OPS=1
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include make/module.mk
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