131 lines
4.6 KiB
ArmAsm
131 lines
4.6 KiB
ArmAsm
/*
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* Copyright (c) 2014, Google Inc. All rights reserved
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <asm.h>
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#include <arch/ops.h>
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#include <arch/defines.h>
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#include <arch/asm_macros.h>
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.text
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.macro cache_range_op, cache op
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add x2, x0, x1 // calculate the end address
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bic x3, x0, #(CACHE_LINE-1) // align the start with a cache line
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.Lcache_range_op_loop\@:
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\cache \op, x3
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add x3, x3, #CACHE_LINE
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cmp x3, x2
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blo .Lcache_range_op_loop\@
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dsb sy
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.endm
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/* void arch_flush_cache_range(addr_t start, size_t len); */
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FUNCTION(arch_clean_cache_range)
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cache_range_op dc cvac // clean cache to PoC by MVA
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ret
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/* void arch_flush_invalidate_cache_range(addr_t start, size_t len); */
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FUNCTION(arch_clean_invalidate_cache_range)
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cache_range_op dc civac // clean & invalidate dcache to PoC by MVA
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ret
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/* void arch_invalidate_cache_range(addr_t start, size_t len); */
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FUNCTION(arch_invalidate_cache_range)
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cache_range_op dc ivac // invalidate dcache to PoC by MVA
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ret
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/* void arch_sync_cache_range(addr_t start, size_t len); */
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FUNCTION(arch_sync_cache_range)
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cache_range_op dc cvau // clean dcache to PoU by MVA
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cache_range_op ic ivau // invalidate icache to PoU by MVA
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ret
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/* void arch_disable_cache(uint flags); */
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FUNCTION(arch_disable_cache)
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// LK runs in EL1
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/* Disable iCache and dCache */
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.inEL1:
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mrs x4, sctlr_el1
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bic x4, x4, #(1 << 12) // Disable iCache
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bic x4, x4, #(1 << 2) // Disable dCache
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msr sctlr_el1, x4
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isb
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/* Clean and Invalidate dCache */
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mrs x0, CLIDR_EL1
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and w3, w0, #0x07000000 // Bits: 26:24 Level of Coherence
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lsr w3, w3, #23 // Store 2 x LoC in W3
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cbz w3, Finished // If 0, we are done
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mov w10, #0 // store 2x cache level (since csselr starts at bit 1)
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mov w8, #1
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Loop1:
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add w2, w10, w10, lsr #1 // Calculate 3x cache level a(w10 + 2w10 = 3w10)
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lsr w1, w0, w2 // read cType (cache type)
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and w1, w1, #0x7 // mask 3-bits
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cmp w1, #2 // types >=2 include data cache
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b.lt Skip // skip if no data cache implemented
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msr csselr_el1, x10 // select the cache level
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isb // sync
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mrs x1, ccsidr_el1 // read ccsidr (current cache size id)
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and w2, w1, #0x7 // w2 = log2(linesize) - 4
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add w2, w2, #4 // w2 = log2(linesize)
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ubfx w4, w1, #3, #10 // w4 = way number (associativity)
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clz w5, w4 // w5 = 32 - log2(ways), bit pos in dc operand
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lsl w9, w4, w5 // w9 = max way number, aligned to position in dc operand
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lsl w16, w8, w5 // w16 = amount to decrement way number per iteration
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Loop2:
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ubfx w7, w1, #13, #15 // w7 = max set number
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lsl w7, w7, w2 // w7= max set number, aligned to position in dc operand
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lsl w17, w8, w2 // w17 = amount to decrement set number per iteration
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Loop3:
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orr w11, w10, w9 // w11 = combine way number, cache number and set num for dc operand
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orr w11, w11, w7
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dc cisw, x11 // perform clean by set and way
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subs w7, w7, w17 // decrement set number
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b.ge Loop3
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subs x9, x9, x16 // decrement way number
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b.ge Loop2
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Skip:
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add w10, w10, #2
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cmp w3, w10
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dsb sy
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b.gt Loop1
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Finished:
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/* invalidate iCache*/
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ic ialluis
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isb
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/* invalidate TLB */
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tlbi vmalle1
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dsb sy
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isb
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ret
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