b433d4582d
These cpus only support a simple 16 bit offset from PC, so cannot use it in start.S to compute a large offset. This is okay, because the code that needs it is only for cpus with an MMU, which these dont have.
177 lines
5.1 KiB
ArmAsm
177 lines
5.1 KiB
ArmAsm
/*
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* Copyright (c) 2021 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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.section .text.boot
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FUNCTION(_start)
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// load the first 4 args that were pushed on whatever stack we have
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// NOTE: assumes stack is pointing at at least readable memory
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movl %sp@(4),%d4
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movl %sp@(8),%d5
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movl %sp@(12),%d6
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movl %sp@(16),%d7
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#if ARCH_DO_RELOCATION
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lea %pc@(_start),%a0 // load the current address using PC relative addressing mode
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movl #_start,%a1 // load the same symbol absolutely
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cmpal %a0,%a1
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beqs bss_clear
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// load the end address for loop termination
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movl #_end,%a2
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// copy forwards
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// NOTE: assumes the source and target do not overlap
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0:
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movel %a0@+,%a1@+
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cmpal %a1,%a2
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bne 0b
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// branch to the new location
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movl #bss_clear,%a0
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jmp %a0@
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#endif
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// clear bss
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bss_clear:
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#if M68K_CPU >= 68020
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// 020 and above have a full 32bit PC relative addressing mode.
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// Since we may be using a mmu in this case, we may be operating in physical address space,
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// so we need to use PC relative addressing to get the right addresses.
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lea %pc@(__bss_start),%a0
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lea %pc@(__bss_end),%a1
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#else
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// We wont be using an MMU on 68000 and 68010, so we can use absolute addresses.
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movl __bss_start,%a0
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movl __bss_end,%a1
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#endif
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cmpl %a0,%a1
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beqs 1f
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// zero 4 bytes at a time
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0:
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clrl %a0@+
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cmpal %a1,%a0
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bne 0b
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1:
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#if M68K_MMU == 68040
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init_mmu_68040:
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// Set up DTTR0 and ITTR0 to map 0x00000000 - 0x3FFFFFFF (1GB) to 0x00000000
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// Logical address base: 0x00000000, mask 0x3f000000, enable, supervisor, cacheble, copyback
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movl #0x003fa020,%d0
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movec %d0,%dtt0
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movec %d0,%itt0
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// Set up an mapping of [0, MEMSIZE) to [KERNEL_ASPACE_BASE, KERNEL_ASPACE_BASE + MEMSIZE)
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// Set up L0 entries
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lea %pc@(_root_page_table),%a0
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addl #(KERNEL_ASPACE_BASE / L0_ENTRY_RANGE * 4),%a0 // offset into the middle of the L0 table for KERNEL_ASPACE_BASE
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movl #L0_ENTRIES,%d0
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lea %pc@(_l1_tables),%a1 // get pointer to L1 tables
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addl #0x00000003,%a1 // mark it valid
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.Ll0_loop:
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movl %a1,%a0@ // store it in the L0 table
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addl #4,%a0 // advance to next L0 entry
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addl #L1_PGTABLE_ENTRIES * 4,%a1 // advance to next L1 table
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subl #1,%d0
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bne .Ll0_loop
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// Set up L1 entries
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lea %pc@(_l1_tables),%a0
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movl #L1_ENTRIES,%d0
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lea %pc@(_l2_tables),%a1 // get pointer to L2 table
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addl #0x00000003,%a1 // mark it valid
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.Ll1_loop:
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movl %a1,%a0@
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addl #4,%a0
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addl #L2_PGTABLE_ENTRIES * 4,%a1 // advance to next L1 table
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subl #1,%d0
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bne .Ll1_loop
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// Set up L2 entries
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lea %pc@(_l2_tables),%a0
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movl #L2_ENTRIES,%d0
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movl #0x000000083,%d1 // address 0, supervisor, writable, present
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.L2_loop:
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movl %d1,%a0@ // read the current entry
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addl #4,%a0 // advance to next L2 entry
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addl #PAGE_SIZE,%d1 // advance to next page
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subl #1,%d0
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bne .L2_loop
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// set the supervisor root pointer
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lea %pc@(_root_page_table),%a0
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movec %a0,%srp
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movec %a0,%urp
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// enable the mmu
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movl #(1<<15),%d0
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movec %d0,%tc
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// Branch to the high memory area
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movl #.Lhigh_target,%a0
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jmp %a0@
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.Lhigh_target:
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// Turn off DTTR0 and ITTR0
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clrl %d0
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movec %d0,%dtt0
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movec %d0,%itt0
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#endif
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// load the initial stack pointer
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lea _default_stack_top,%sp
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// branch into C land with 4 args off the previous stack
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movl %d7,%sp@-
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movl %d6,%sp@-
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movl %d5,%sp@-
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movl %d4,%sp@-
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jsr lk_main
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// if we return from main just loop forever
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bra .
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END_FUNCTION(_start)
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.bss
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.balign 4
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_default_stack_base:
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.skip 4096
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_default_stack_top:
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#if M68K_MMU == 68040
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// Define space for page tables to set up a mapping of MEMSIZE bytes of memory at KERNEL_ASPACE_BASE
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.equ PAGE_SIZE, 4096
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.equ L0_PGTABLE_ENTRIES, 128 // 7 bits
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.equ L0_ENTRY_RANGE, (1<<25) // each L0 entry covers 32MB
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.equ L1_PGTABLE_ENTRIES, 128 // 7 bits
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.equ L1_ENTRY_RANGE, (1<<18) // each L1 entry covers 256KB
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.equ L2_PGTABLE_ENTRIES, 64 // 6 bits
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// Number of entries at each level to fill in order to cover MEMSIZE,
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// rounded up to the next L0 entry range so all of the L1 and L2 page tables are fully used.
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.equ MEMSIZE_ROUNDED, (MEMSIZE + L0_ENTRY_RANGE - 1) & ~(L0_ENTRY_RANGE - 1)
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.equ L0_ENTRIES, MEMSIZE_ROUNDED / L0_ENTRY_RANGE
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.equ L1_ENTRIES, MEMSIZE_ROUNDED / L1_ENTRY_RANGE
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.equ L2_ENTRIES, MEMSIZE_ROUNDED / PAGE_SIZE
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.balign 4096
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_root_page_table:
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.skip L0_PGTABLE_ENTRIES * 4 // 128 entries, 4 bytes each
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.balign 4096
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_l1_tables:
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.skip L1_ENTRIES * 4 // 4 bytes each, one per 256KB section of memory
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.balign 4096
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_l2_tables:
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.skip L2_ENTRIES * 4 // 4 bytes each, one per page of memory
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#endif // M68K_MMU == 68040
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