ae5200595c
The virt machine is a generic target, much like the arm virt machine. Intended to be simple to use and a good target to run large systems like linux on. At the moment simply support booting and simple uart and timer support.
69 lines
1.7 KiB
C
69 lines
1.7 KiB
C
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <assert.h>
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#include <lk/compiler.h>
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#include <lk/trace.h>
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#include <arch/riscv.h>
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#include <kernel/thread.h>
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#define LOCAL_TRACE 0
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// keep in sync with asm.S
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struct riscv_short_iframe {
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ulong mepc;
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ulong mstatus;
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ulong ra;
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ulong a0;
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ulong a1;
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ulong a2;
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ulong a3;
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ulong a4;
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ulong a5;
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ulong a6;
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ulong a7;
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ulong t0;
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ulong t1;
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ulong t2;
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ulong t3;
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ulong t4;
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ulong t5;
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ulong t6;
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};
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extern enum handler_return riscv_platform_irq(void);
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void riscv_exception_handler(ulong cause, ulong epc, struct riscv_short_iframe *frame) {
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LTRACEF("cause %#lx epc %#lx mstatus %#lx\n", cause, epc, frame->mstatus);
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DEBUG_ASSERT(arch_ints_disabled());
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DEBUG_ASSERT(frame->mstatus & RISCV_STATUS_MPIE);
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enum handler_return ret = INT_NO_RESCHEDULE;
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switch (cause) {
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case 0x80000007: // machine timer interrupt
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ret = riscv_timer_exception();
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break;
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case 0x8000000b: // machine external interrupt
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ret = riscv_platform_irq();
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break;
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default:
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TRACEF("unhandled cause %#lx, epc %#lx, mtval %#lx\n", cause, epc, riscv_csr_read(mtval));
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panic("stopping");
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}
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DEBUG_ASSERT(arch_ints_disabled());
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DEBUG_ASSERT(frame->mstatus & RISCV_STATUS_MPIE);
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if (ret == INT_RESCHEDULE) {
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thread_preempt();
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}
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DEBUG_ASSERT(arch_ints_disabled());
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DEBUG_ASSERT(frame->mstatus & RISCV_STATUS_MPIE);
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}
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