acfe991c7f
Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
25 lines
597 B
C
25 lines
597 B
C
/*
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* Copyright (c) 2019 Elliot Berman
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#define SIFIVE_IRQ_UART0 4
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#define SIFIVE_IRQ_UART1 5
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#define SIFIVE_NUM_IRQS 53
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#define CLINT_BASE 0x02000000
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#define PLIC_BASE 0x0c000000
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#define PRCI_BASE 0x10000000
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#define UART0_BASE 0x10010000
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#define UART1_BASE 0x10011000
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#define PWM0_BASE 0x10020000
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#define PWM1_BASE 0x10021000
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#define GPIO_BASE 0x10060000
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#define PLIC_HART_IDX(hart) ((hart) ? ((2 * (hart)) - 1) : 0)
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