acfe991c7f
Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
29 lines
665 B
C
29 lines
665 B
C
/*
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* Copyright (c) 2018 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#define SIFIVE_IRQ_UART0 3
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#define SIFIVE_IRQ_UART1 4
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#define SIFIVE_NUM_IRQS 127
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#define CLINT_BASE 0x02000000
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#define PLIC_BASE 0x0c000000
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#define PRCI_BASE 0x10008000
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#define GPIO_BASE 0x10012000
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#define UART0_BASE 0x10013000
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#define GPIO_REG_VALUE 0
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#define GPIO_REG_INPUT_EN 1
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#define GPIO_REG_OUTPUT_EN 2
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#define GPIO_REG_PORT 3
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#define GPIO_REG_IOF_EN 14
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#define GPIO_REG_IOF_SEL 15
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#define PLIC_HART_IDX(hart) 0
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