Elliot Berman
acfe991c7f
[arch][riscv] Expose RISC-V mp kernel start
...
Support mp lk start on RISC-V. Several changes throughout were required:
- Add signal in asm start to force secondary harts to wait for bss to be
cleared.
- Use mhartid in arch_curr_cpu_num, PLIC, and CLINT
- Use tp register as thread pointer instead of global variable.
- Support sending IPIs between harts using CLINT
- Add spinlock implementation
2020-01-16 23:06:28 -08:00
..
2015-09-01 13:26:27 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-13 16:09:27 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-13 16:56:33 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-11-02 14:19:36 -07:00
2016-08-23 12:28:28 -07:00
2016-08-23 12:28:28 -07:00
2020-01-16 23:06:28 -08:00
2020-01-16 23:06:28 -08:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-11-18 15:36:28 -08:00
2019-07-05 17:22:23 -07:00
2018-03-16 15:05:10 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2019-07-05 17:22:23 -07:00
2012-08-31 15:52:24 -07:00