acfe991c7f
Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
91 lines
1.9 KiB
ArmAsm
91 lines
1.9 KiB
ArmAsm
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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#include <arch/defines.h>
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#include "config.h"
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.section ".text.boot"
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FUNCTION(_start)
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.option push
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.option norelax
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// set the global pointer
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la gp, __global_pointer$
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.option pop
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// if our hart isnt 0, trap the cpu
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csrr t0, mhartid
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// set the default stack
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la sp, default_stack_top
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// default stack locations for each hart:
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// LOW ------------ HIGH
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// [hart2][hart1][hart0]
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li t1, ARCH_DEFAULT_STACK_SIZE
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mul t1, t1, a0
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sub sp, sp, t1
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// everyone stores zero in _boot_status
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la t5, _boot_status
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sw zero, (t5)
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bnez t0, .Lsecondary_trap
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#if ARCH_RISCV_TWOSEGMENT
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// copy preinitialized data from flash to memory
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la t0, __data_start_rom
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la t1, __data_start
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la t2, __data_end
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beq t0, t1, 1f
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0:
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lw t3, (t0)
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sw t3, (t1)
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add t0, t0, 4
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add t1, t1, 4
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bne t1, t2, 0b
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#endif
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// zero bss
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1:
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la t0, __bss_start
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la t1, __bss_end
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0:
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sw x0, (t0)
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add t0, t0, 4
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bne t0, t1, 0b
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// Release any other harts into riscv_secondary_entry
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fence w, w
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add t0, zero, 1
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sw t0, (t5)
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// call main
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jal lk_main
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// should never return here
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j .
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.Lsecondary_trap:
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#if WITH_SMP
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// wait for _boot_status to be nonzero, then go into riscv_secondary_entry
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lw t0, (t5)
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beqz t0, .Lsecondary_trap
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jal riscv_secondary_entry
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#else
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wfi
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j .
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#endif
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.bss
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.align 4
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LOCAL_DATA(default_stack)
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.skip ARCH_DEFAULT_STACK_SIZE * SMP_MAX_CPUS
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LOCAL_DATA(default_stack_top)
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LOCAL_DATA(_boot_status)
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.dword
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