acfe991c7f
Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
67 lines
1.5 KiB
C
67 lines
1.5 KiB
C
/*
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* Copyright (c) 2019 Elliot Berman
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/reg.h>
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#include <lk/debug.h>
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#include <lk/trace.h>
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#include <lk/err.h>
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#include <arch/mp.h>
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#define LOCAL_TRACE 0
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static mp_ipi_t ipi_data[SMP_MAX_CPUS];
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extern void clint_ipi_send(unsigned long target_hart);
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extern void clint_ipi_clear(unsigned long target_hart);
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status_t arch_mp_send_ipi(mp_cpu_mask_t target, mp_ipi_t ipi) {
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LTRACEF("target 0x%x, ipi %u\n", target, ipi);
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unsigned long cur_hart = riscv_csr_read(mhartid);
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unsigned long h = 0;
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mp_cpu_mask_t m = target;
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for (; h < SMP_MAX_CPUS && m; h++, m >>= 1) {
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if ((m & 1) && (h != cur_hart)) {
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ipi_data[h] = ipi;
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asm volatile(" fence iorw,iorw");
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clint_ipi_send(h);
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}
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}
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if(target & (1 << cur_hart)) {
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clint_ipi_send(cur_hart);
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}
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return NO_ERROR;
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}
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enum handler_return riscv_software_exception(void) {
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clint_ipi_clear(riscv_csr_read(mhartid));
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asm volatile(" fence ir,ir");
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mp_ipi_t reason = ipi_data[riscv_current_hart()];
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ipi_data[riscv_current_hart()] = 0;
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switch (reason) {
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case MP_IPI_RESCHEDULE:
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return INT_RESCHEDULE;
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case MP_IPI_GENERIC:
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break;
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default:
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TRACEF("unhandled ipi cause %#x, hartid %#lx\n", reason, riscv_current_hart());
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panic("stopping");
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break;
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}
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return INT_NO_RESCHEDULE;
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}
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void arch_mp_init_percpu(void) {
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riscv_csr_set(mie, RISCV_MIE_MSIE);
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}
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