Travis Geiselbrecht ab0e1fd3a1 [arch][x86][exceptions] clean up the exception handlers ...

For both 32 and 64bit x86, have each of the exception stubs which push a
few words and branch to the common isr routine be simply 16 byte aligned
to make it easy to calculate the offset from the main isr table. This
cleans up some complexity that was actually broken for interrupts >= 0x80.

Also:
-Switch alignment directives to .balign
-Expand the x86-32 exception table to a full 256
-Remove an extraneous define
-Make sure the IDT is 8 or 16 byte aligned
-Use END_DATA and END_FUNCTION in the exception and gdt asm files

2024-03-10 21:50:01 -07:00

..

32

[arch][x86][exceptions] clean up the exception handlers

2024-03-10 21:50:01 -07:00

64

[arch][x86][exceptions] clean up the exception handlers

2024-03-10 21:50:01 -07:00

include/arch

[arch][x86] Change the cache line size to 64 bytes

2023-05-20 17:46:24 -07:00

arch.c

[arch][x86][mmu] update how mmu code accesses physical pages

2022-11-02 23:48:49 -07:00

cache.c

[license] replace the longer full MIT license with a shorter one

2019-07-05 17:22:23 -07:00

descriptor.c

[license] replace the longer full MIT license with a shorter one

2019-07-05 17:22:23 -07:00

faults.c

[arch][x86][32] fix a bug in the exception report

2022-10-19 20:22:10 -07:00

feature.c

[arch][x86] clean up a bit of the cpuid detection

2022-10-19 20:03:49 -07:00

fpu.c

[arch][x86] clean up of mmu code

2022-10-23 20:37:33 -07:00

gdt.S

[arch][x86][exceptions] clean up the exception handlers

2024-03-10 21:50:01 -07:00

rules.mk

[arch][x86] general cleanup

2022-11-02 23:02:24 -07:00

thread.c

[license] replace the longer full MIT license with a shorter one

2019-07-05 17:22:23 -07:00

toolchain.mk

[build][arch] have arm, arm64, and x86 resort to a default toolchain

2021-09-18 16:52:38 -07:00