Travis Geiselbrecht a8e460f847 [arch][riscv] add -misa-spec=2.2 to the compile switches ...

This works around an issue with newer compilers that default to an
earlier ISA spec that doesn't by default include the zicsr extension by
default.

If the compiler doesn't support the switch, then it's assumed that it
has the extension by default, as older gcc compilers did.

2022-05-22 15:14:34 -07:00

..

include/arch

[arch][riscv] C++ header guard the core riscv header

2022-05-13 01:06:58 -07:00

arch.c

[arch][riscv] using a new trick utilize real instructions to zero fpu state

2022-03-12 17:39:00 -08:00

asm.S

[arch][riscv] move the iframe definitions into a separate header and add syscall support

2021-04-11 03:38:03 -07:00

exceptions.c

[arch][warnings] fix -Wmissing-declarations warnings

2021-10-21 23:08:38 -07:00

fpu_asm.S

[arch][riscv] using a new trick utilize real instructions to zero fpu state

2022-03-12 17:39:00 -08:00

linker-onesegment.ld

[arch][riscv] fix bug with gcc 10.2 & binutils 2.35 with section padding

2020-12-09 01:59:16 -08:00

linker-twosegment.ld

[arch][riscv] fix bug with gcc 10.2 & binutils 2.35 with section padding

2020-12-09 01:59:16 -08:00

mmu.cpp

[libc][assert] add __PRINTFLIKE to assert_fail_msg()

2021-11-12 22:07:14 -08:00

mp.c

[arch][warnings] fix -Wmissing-declarations warnings

2021-10-21 23:08:38 -07:00

riscv_priv.h

[arch][warnings] fix -Wmissing-declarations warnings

2021-10-21 23:08:38 -07:00

rules.mk

[arch][riscv] add -misa-spec=2.2 to the compile switches

2022-05-22 15:14:34 -07:00

sbi.c

[arch][riscv] more work on riscv MMU code

2021-03-30 02:48:59 -07:00

spinlock.c

[arch][riscv] spiff up the spinlock code a bit

2021-03-30 02:48:59 -07:00

start.S

[arch][riscv][mmu] permanently allocate top level buffers to help keep user space aspaces in sync

2021-04-08 23:55:27 -07:00

thread.c

[arch][riscv] make sure the stack is 16 byte aligned for new threads

2020-05-03 19:34:32 -07:00

time.c

[arch][riscv] add timer hack back

2020-01-16 23:10:35 -08:00