197 lines
8.0 KiB
C
197 lines
8.0 KiB
C
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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/*
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* COPYRIGHT(c) 2015 STMicroelectronics
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#include <lk/err.h>
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#include <lk/debug.h>
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#include <lk/trace.h>
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#include <target.h>
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#include <lk/compiler.h>
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#include <dev/gpio.h>
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#include <platform/stm32.h>
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#define SRAM_OK ((uint8_t)0x00)
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#define SRAM_ERROR ((uint8_t)0x01)
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/* #define SRAM_MEMORY_WIDTH FMC_NORSRAM_MEM_BUS_WIDTH_8*/
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#define SRAM_MEMORY_WIDTH FMC_NORSRAM_MEM_BUS_WIDTH_16
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#define SRAM_BURSTACCESS FMC_BURST_ACCESS_MODE_DISABLE
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//#define SRAM_BURSTACCESS FMC_BURST_ACCESS_MODE_ENABLE
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#define SRAM_WRITEBURST FMC_WRITE_BURST_DISABLE
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//#define SRAM_WRITEBURST FMC_WRITE_BURST_ENABLE
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#define CONTINUOUSCLOCK_FEATURE FMC_CONTINUOUS_CLOCK_SYNC_ONLY
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//#define CONTINUOUSCLOCK_FEATURE FMC_CONTINUOUS_CLOCK_SYNC_ASYNC
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/* DMA definitions for SRAM DMA transfer */
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#define __SRAM_DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
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#define __SRAM_DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
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#define SRAM_DMAx_CHANNEL DMA_CHANNEL_0
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#define SRAM_DMAx_STREAM DMA2_Stream4
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#define SRAM_DMAx_IRQn DMA2_Stream4_IRQn
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#define SRAM_DMAx_IRQHandler DMA2_Stream4_IRQHandler
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static SRAM_HandleTypeDef sramHandle;
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static FMC_NORSRAM_TimingTypeDef Timing;
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/**
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* @brief Initializes SRAM MSP.
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* @param hsram: SRAM handle
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* @retval None
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*/
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static void BSP_SRAM_MspInit(SRAM_HandleTypeDef *hsram, void *Params) {
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static DMA_HandleTypeDef dma_handle;
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GPIO_InitTypeDef gpio_init_structure;
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/* Enable FMC clock */
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__HAL_RCC_FMC_CLK_ENABLE();
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/* Enable chosen DMAx clock */
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__SRAM_DMAx_CLK_ENABLE();
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/* Enable GPIOs clock */
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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/* Common GPIO configuration */
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gpio_init_structure.Mode = GPIO_MODE_AF_PP;
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gpio_init_structure.Pull = GPIO_PULLUP;
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gpio_init_structure.Speed = GPIO_SPEED_HIGH;
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gpio_init_structure.Alternate = GPIO_AF12_FMC;
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/* GPIOD configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 |\
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\
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GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOD, &gpio_init_structure);
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/* GPIOE configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3| GPIO_PIN_4 | GPIO_PIN_7 |\
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GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOE, &gpio_init_structure);
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/* GPIOF configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
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GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOF, &gpio_init_structure);
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/* GPIOG configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
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GPIO_PIN_5 | GPIO_PIN_10;
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HAL_GPIO_Init(GPIOG, &gpio_init_structure);
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/* Configure common DMA parameters */
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dma_handle.Init.Channel = SRAM_DMAx_CHANNEL;
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dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
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dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
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dma_handle.Init.MemInc = DMA_MINC_ENABLE;
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dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
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dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
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dma_handle.Init.Mode = DMA_NORMAL;
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dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
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dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
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dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
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dma_handle.Instance = SRAM_DMAx_STREAM;
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/* Associate the DMA handle */
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__HAL_LINKDMA(hsram, hdma, dma_handle);
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/* Deinitialize the Stream for new transfer */
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HAL_DMA_DeInit(&dma_handle);
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/* Configure the DMA Stream */
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HAL_DMA_Init(&dma_handle);
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/* NVIC configuration for DMA transfer complete interrupt */
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HAL_NVIC_SetPriority(SRAM_DMAx_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(SRAM_DMAx_IRQn);
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}
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/**
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* @brief Initializes the SRAM device.
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* @retval SRAM status
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*/
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uint8_t BSP_SRAM_Init(void) {
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static uint8_t sram_status = SRAM_ERROR;
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/* SRAM device configuration */
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sramHandle.Instance = FMC_NORSRAM_DEVICE;
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sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
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/* SRAM device configuration */
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/* Timing configuration derived from system clock (up to 216Mhz)
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for 108Mhz as SRAM clock frequency */
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Timing.AddressSetupTime = 2;
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Timing.AddressHoldTime = 1;
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Timing.DataSetupTime = 2;
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Timing.BusTurnAroundDuration = 1;
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Timing.CLKDivision = 2;
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Timing.DataLatency = 2;
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Timing.AccessMode = FMC_ACCESS_MODE_A;
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sramHandle.Init.NSBank = FMC_NORSRAM_BANK3;
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sramHandle.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
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sramHandle.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
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sramHandle.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
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sramHandle.Init.BurstAccessMode = SRAM_BURSTACCESS;
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sramHandle.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
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sramHandle.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
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sramHandle.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
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sramHandle.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
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sramHandle.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
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sramHandle.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
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sramHandle.Init.WriteBurst = SRAM_WRITEBURST;
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sramHandle.Init.ContinuousClock = CONTINUOUSCLOCK_FEATURE;
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/* SRAM controller initialization */
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BSP_SRAM_MspInit(&sramHandle, NULL); /* __weak function can be rewritten by the application */
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if (HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK) {
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sram_status = SRAM_ERROR;
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} else {
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sram_status = SRAM_OK;
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}
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return sram_status;
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}
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