124 lines
3.7 KiB
C
124 lines
3.7 KiB
C
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/trace.h>
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#include <lk/debug.h>
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#include <stdint.h>
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#include <lk/bits.h>
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#include <arch.h>
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#include <arch/mips.h>
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#include <platform.h>
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#define LOCAL_TRACE 0
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void arch_early_init(void) {
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LTRACE;
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/* configure the vector table */
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uint32_t temp = mips_read_c0_status();
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temp &= ~(1<<22); /* unset BEV, which moves vectors to 0x80000000 */
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temp &= ~(1<<2); /* clear ERL */
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/* mask all of the irq handlers */
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temp &= ~(1<<8); // IM0
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temp &= ~(1<<9); // IM1
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temp &= ~(1<<10); // IM2
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temp &= ~(1<<11); // IM3
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temp &= ~(1<<12); // IM4
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temp &= ~(1<<13); // IM5
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temp &= ~(1<<14); // IM6
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temp &= ~(1<<15); // IM7
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temp &= ~(1<<16); // IM8
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temp &= ~(1<<18); // IM9 (note the bit gap)
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mips_write_c0_status(temp);
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/* set ebase */
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mips_write_c0_ebase(MEMBASE);
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/* make sure we take exceptions in 32bit mips mode */
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mips_write_c0_config3(mips_read_c0_config3() & ~(1<<16));
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/* set vectored mode */
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temp = mips_read_c0_intctl();
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temp &= ~(0b1111 << 5);
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temp |= 1 << 5; /* 32 byte spacing */
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STATIC_ASSERT(VECTORED_OFFSET_SHIFT == 32);
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mips_write_c0_intctl(temp);
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temp = mips_read_c0_cause();
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temp |= (1<<23); /* IV vectored mode */
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mips_write_c0_cause(temp);
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}
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void arch_init(void) {
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LTRACE;
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printf("MIPS registers:\n");
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printf("\tPRId 0x%x\n", mips_read_c0_prid());
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printf("\tconfig 0x%x\n", mips_read_c0_config());
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printf("\tconfig1 0x%x\n", mips_read_c0_config1());
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printf("\tconfig2 0x%x\n", mips_read_c0_config2());
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printf("\tconfig3 0x%x\n", mips_read_c0_config3());
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printf("\tconfig4 0x%x\n", mips_read_c0_config4());
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printf("\tconfig5 0x%x\n", mips_read_c0_config5());
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printf("\tconfig6 0x%x\n", mips_read_c0_config6());
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printf("\tconfig7 0x%x\n", mips_read_c0_config7());
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printf("\tstatus 0x%x\n", mips_read_c0_status());
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uint32_t intctl = mips_read_c0_intctl();
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printf("\tintctl 0x%x\n", intctl);
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printf("\t\tIPTI 0x%lx\n", BITS_SHIFT(intctl, 31, 29));
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printf("\t\tIPPCI 0x%lx\n", BITS_SHIFT(intctl, 28, 26));
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printf("\t\tIPFDC 0x%lx\n", BITS_SHIFT(intctl, 25, 23));
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printf("\tsrsctl 0x%x\n", mips_read_c0_srsctl());
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printf("\tebase 0x%x\n", mips_read_c0_ebase());
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printf("\tcount 0x%x\n", mips_read_c0_count());
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printf("\tcompare 0x%x\n", mips_read_c0_compare());
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__asm__ volatile("syscall");
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LTRACE_EXIT;
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}
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void arch_idle(void) {
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asm volatile("wait");
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}
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void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) {
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PANIC_UNIMPLEMENTED;
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}
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void mips_enable_irq(uint num) {
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uint32_t temp = mips_read_c0_status();
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if (num < 9) {
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temp |= (1 << (num + 8));
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} else if (num == 9) {
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temp |= (1 << 18);
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}
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mips_write_c0_status(temp);
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}
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void mips_disable_irq(uint num) {
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uint32_t temp = mips_read_c0_status();
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if (num < 9) {
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temp &= ~(1 << (num + 8));
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} else if (num == 9) {
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temp &= ~(1 << 18);
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}
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mips_write_c0_status(temp);
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}
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/* unimplemented cache operations */
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void arch_disable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_enable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_clean_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_clean_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_sync_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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