bd12570f3c
Mostly rewrote to be cleaner and more obvious what it's doing, but turns out the real problem was a lack of "memory" and/or volatile. In one of the test cases the compiler was rearranging the arch_ints_disabled() check.
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/*
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* Copyright (c) 2021 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#include <lk/compiler.h>
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#include <lk/debug.h>
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__BEGIN_CDECLS
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#define M68K_SR_IPM_MASK ((0b111 << 8)) // interrupt priority mask
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static inline void arch_enable_ints(void) {
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asm volatile("andi %0, %%sr" :: "i" (~M68K_SR_IPM_MASK) : "memory");
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}
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static inline void arch_disable_ints(void) {
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asm volatile("ori %0, %%sr" :: "i" (M68K_SR_IPM_MASK) : "memory");
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}
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static inline bool arch_ints_disabled(void) {
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uint16_t sr;
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asm volatile("move %%sr, %0" : "=r"(sr) :: "memory");
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// if the IPM is != 0, consider interrupts disabled
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return (sr & M68K_SR_IPM_MASK);
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}
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// use a global pointer to store the current_thread
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extern struct thread *_current_thread;
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static inline struct thread *arch_get_current_thread(void) {
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return _current_thread;
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}
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static inline void arch_set_current_thread(struct thread *t) {
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_current_thread = t;
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}
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static inline ulong arch_cycle_count(void) { return 0; }
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static inline uint arch_curr_cpu_num(void) {
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return 0;
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}
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// TODO: see if there's a proper (or required) memory barrier on 68k
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#define mb() CF
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#define wmb() CF
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#define rmb() CF
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#define smp_mb() CF
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#define smp_wmb() CF
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#define smp_rmb() CF
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__END_CDECLS
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