91128ad729
- Add a percpu structure for each cpu, akin to x86-64 and riscv. Pointed to by x18, which is now reserved for this in the kernel. Tweaked exception and context switch routines to leave x18 alone. - Remove the cpu-trapping spinlock logic that is unused in mainline, probably. (Can add a new version of it back if it's necessary). - Switch fdtwalk helper to using the newer, cleaner way of initializing secondaries using the PSCI CPU_ON argument that should be pretty standard on modern implementations. (Possibly an issue with old firmware). - Remove the notion of computing the cpu ID from the Affinity levels, which doesn't really work properly on modern ARM CPUs which more or less abandoned the logical meaning of AFFn.
26 lines
617 B
C
26 lines
617 B
C
/*
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* Copyright (c) 2025 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#include <sys/types.h>
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#include <lk/compiler.h>
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__BEGIN_CDECLS
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void arm64_early_init_percpu(void);
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// void riscv_early_init_percpu(void);
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// void riscv_init_percpu(void);
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// void riscv_boot_secondaries(void);
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// void riscv_configure_percpu_mp_early(uint hart_id, uint cpu_num);
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// void riscv_early_mmu_init(void);
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// void riscv_mmu_init(void);
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// void riscv_mmu_init_secondaries(void);
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__END_CDECLS
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