90dc9e50ef
Had rotted a bit. Had to reimplement a few tweaks. Also generally #if out a lot of the SMP code when unused on riscv.
81 lines
1.9 KiB
C
81 lines
1.9 KiB
C
/*
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* Copyright (c) 2019 Elliot Berman
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/reg.h>
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#include <lk/debug.h>
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#include <lk/trace.h>
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#include <lk/err.h>
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#include <arch/ops.h>
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#include <arch/mp.h>
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#if WITH_SMP
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#define LOCAL_TRACE 0
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int hart_cpu_map[SMP_MAX_CPUS] = { [0 ... SMP_MAX_CPUS-1] = -1 };
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static mp_ipi_t ipi_data[SMP_MAX_CPUS];
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extern void clint_ipi_send(unsigned long target_hart);
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extern void clint_ipi_clear(unsigned long target_hart);
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status_t arch_mp_send_ipi(mp_cpu_mask_t target, mp_ipi_t ipi) {
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LTRACEF("target 0x%x, ipi %u\n", target, ipi);
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unsigned long hart_mask = 0;
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unsigned long c = 0, h;
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mp_cpu_mask_t m = target;
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for (; c < SMP_MAX_CPUS && m; c++, m >>= 1) {
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h = hart_cpu_map[c];
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if (m & 1) {
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hart_mask |= (1 << h);
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}
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// TODO: set the ipi_data based on the incoming ipi
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}
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asm volatile(" fence iorw,iorw");
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#if RISCV_M_MODE
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clint_send_ipis(&hart_mask);
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#else
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sbi_send_ipis(&hart_mask);
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#endif
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return NO_ERROR;
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}
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enum handler_return riscv_software_exception(void) {
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#if RISCV_M_MODE
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clint_ipi_clear(riscv_current_hart());
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#else
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sbi_clear_ipi();
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#endif
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asm volatile(" fence ir,ir");
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mp_ipi_t reason = ipi_data[riscv_current_hart()];
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ipi_data[riscv_current_hart()] = 0;
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switch (reason) {
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case MP_IPI_RESCHEDULE:
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return INT_RESCHEDULE;
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case MP_IPI_GENERIC:
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break;
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default:
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TRACEF("unhandled ipi cause %#x, hartid %#x\n", reason, riscv_current_hart());
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panic("stopping");
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break;
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}
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return INT_NO_RESCHEDULE;
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}
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void arch_mp_init_percpu(void) {
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dprintf(INFO, "\nRISCV: Booting hart%d (cpu%d)\n", riscv_current_hart(), arch_curr_cpu_num());
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riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_SIE);
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}
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#endif
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