90dc9e50ef
Had rotted a bit. Had to reimplement a few tweaks. Also generally #if out a lot of the SMP code when unused on riscv.
115 lines
3.5 KiB
C
115 lines
3.5 KiB
C
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <assert.h>
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#include <lk/trace.h>
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#include <lk/debug.h>
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#include <stdint.h>
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#include <arch/riscv.h>
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#include <arch/ops.h>
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#include <arch/mp.h>
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#include <lk/init.h>
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#include <lk/main.h>
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#include <platform.h>
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#define LOCAL_TRACE 0
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#if WITH_SMP
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static spin_lock_t boot_cpu_lock = 1;
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static volatile int secondaries_to_init = SMP_MAX_CPUS - 1;
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#endif
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void arch_early_init(void) {
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// set the top level exception handler
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riscv_csr_write(RISCV_CSR_XTVEC, (uintptr_t)&riscv_exception_entry);
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// mask all exceptions, just in case
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riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_IE);
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riscv_csr_clear(RISCV_CSR_XIE, RISCV_CSR_XIE_SIE | RISCV_CSR_XIE_TIE | RISCV_CSR_XIE_EIE);
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// enable cycle counter (disabled for now, unimplemented on sifive-e)
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//riscv_csr_set(mcounteren, 1);
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}
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void arch_init(void) {
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// print some arch info
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dprintf(INFO, "RISCV: mvendorid %#lx marchid %#lx mimpid %#lx mhartid %#x\n",
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riscv_get_mvendorid(), riscv_get_marchid(),
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riscv_get_mimpid(), riscv_current_hart());
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#if RISCV_M_MODE
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dprintf(INFO, "RISCV: misa %#lx\n", riscv_csr_read(RISCV_CSR_MISA));
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#else
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dprintf(INFO, "RISCV: sbi %#lx (%#lx)\n", sbi_call(SBI_GET_SBI_IMPL_ID).value, sbi_call(SBI_GET_SBI_IMPL_VERSION).value);
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#endif
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// enable external interrupts
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riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_EIE);
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#if WITH_SMP
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arch_mp_init_percpu();
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lk_init_secondary_cpus(secondaries_to_init);
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LTRACEF("RISCV: Waiting for %d secondary harts to come up\n", secondaries_to_init);
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/* release the secondary cpus */
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spin_unlock(&boot_cpu_lock);
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// while (secondaries_to_init) arch_idle();
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// spin_lock(&boot_cpu_lock);
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#endif
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}
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#if WITH_SMP
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void riscv_secondary_entry(void) {
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arch_early_init();
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if (unlikely(arch_curr_cpu_num() >= SMP_MAX_CPUS))
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while (1) arch_idle();
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spin_lock(&boot_cpu_lock);
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spin_unlock(&boot_cpu_lock);
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// enable external interrupts
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riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_EIE);
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/* run early secondary cpu init routines up to the threading level */
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lk_init_level(LK_INIT_FLAG_SECONDARY_CPUS, LK_INIT_LEVEL_EARLIEST, LK_INIT_LEVEL_THREADING - 1);
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arch_mp_init_percpu();
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# if RISCV_M_MODE
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dprintf(INFO, "RISCV: secondary hart coming up: mvendorid %#lx marchid %#lx mimpid %#lx mhartid %#x\n",
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riscv_csr_read(mvendorid), riscv_csr_read(marchid),
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riscv_csr_read(mimpid), riscv_current_hart());
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# endif /* RISCV_M_MODE */
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// atomic_add(&secondaries_to_init, -1);
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// arch_mp_send_ipi(1 << 0, MP_IPI_GENERIC); // wake up hart0 to let it know this CPU has come up
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lk_secondary_cpu_entry();
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}
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#endif
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void arch_idle(void) {
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// let the platform/target disable wfi
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#if !RISCV_DISABLE_WFI
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__asm__ volatile("wfi");
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#endif
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}
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void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) {
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PANIC_UNIMPLEMENTED;
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}
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/* unimplemented cache operations */
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void arch_disable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_enable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_clean_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_clean_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_sync_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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