152 lines
3.8 KiB
C
152 lines
3.8 KiB
C
/* swo-uart1.c
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*
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* Copyright 2015 Brian Swetland <swetland@frotz.net>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <string.h>
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#include <debug.h>
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#include <reg.h>
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#include <kernel/thread.h>
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#include <dev/udc.h>
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#include <arch/arm/cm.h>
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#include <platform/lpc43xx-uart.h>
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#include <platform/lpc43xx-gpdma.h>
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#include <platform/lpc43xx-clocks.h>
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#include "rswdp.h"
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#define UART_BASE UART1_BASE
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#define BASE_UART_CLK BASE_UART1_CLK
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extern uint8_t __lpc43xx_main_clock_sel;
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extern uint32_t __lpc43xx_main_clock_mhz;
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#define TXNSIZE 128
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#define TXNCOUNT 4
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typedef struct swo_txn {
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unsigned buf[TXNSIZE/4 + 2];
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struct swo_txn *next;
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udc_request_t *req;
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unsigned busy;
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unsigned num;
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} txn_t;
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static txn_t TXN[TXNCOUNT];
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static txn_t *txwr = TXN;
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static udc_endpoint_t *txept;
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void swo_start_dma(void *ptr);
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static void tx_done(udc_request_t *req, unsigned actual, int status) {
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txn_t *txn = req->context;
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txn->busy = 0;
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if (txwr == txn) {
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// writer wants to write here, and is waiting...
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swo_start_dma(txn->buf + 2);
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}
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}
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void lpc43xx_DMA_IRQ(void) {
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txn_t *txn = txwr;
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arm_cm_irq_entry();
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writel(0xFF, DMA_INTTCCLR);
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writel(0xFF, DMA_INTERRCLR);
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if (udc_request_queue(txept, txn->req)) {
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// failed, usb probably offline, just re-use the buffer
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} else {
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txn->busy = 1;
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txwr = txn = txn->next;
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}
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if (!txn->busy) {
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// if busy, when the usb txn completes, it will start dma then
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swo_start_dma(txn->buf + 2);
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}
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arm_cm_irq_exit(0);
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}
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void swo_init(udc_endpoint_t *_txept) {
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int n;
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txept = _txept;
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for (n = 0; n < TXNCOUNT; n++) {
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TXN[n].req = udc_request_alloc();
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TXN[n].req->context = TXN + n;
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TXN[n].req->buffer = TXN[n].buf;
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TXN[n].req->length = TXNSIZE + 8;
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TXN[n].req->complete = tx_done;
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TXN[n].num = n;
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TXN[n].busy = 0;
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TXN[n].next = TXN + (n + 1);
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TXN[n].buf[0] = RSWD_TXN_ASYNC;
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TXN[n].buf[1] = RSWD_MSG(CMD_SWO_DATA, 0, TXNSIZE);
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}
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TXN[n-1].next = TXN;
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// configure peripheral 4 as uart1_rx
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writel((readl(DMAMUX_REG) & DMAMUX_M(4)) | DMAMUX_P(4, P4_UART1_RX), DMAMUX_REG);
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writel(DMA_CONFIG_EN, DMA_CONFIG);
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NVIC_EnableIRQ(DMA_IRQn);
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// kick off the process with an initial DMA
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swo_start_dma(txwr->buf + 2);
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}
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void swo_start_dma(void *ptr) {
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writel(UART1_BASE + REG_RBR, DMA_SRC(0));
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writel((u32) ptr, DMA_DST(0));
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writel(0, DMA_LLI(0));
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writel(DMA_XFER_SIZE(TXNSIZE) |
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DMA_SRC_BURST(BURST_1) | DMA_DST_BURST(BURST_4) |
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DMA_SRC_BYTE | DMA_DST_WORD | DMA_SRC_MASTER1 | DMA_DST_MASTER0 |
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DMA_DST_INCR | DMA_PROT1 | DMA_TC_IE,
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DMA_CTL(0));
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writel(DMA_ENABLE | DMA_SRC_PERIPH(4) | DMA_FLOW_P2M_DMAc | DMA_TC_IRQ_EN,
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DMA_CFG(0));
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}
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void swo_config(unsigned mhz) {
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if (mhz > 0) {
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uint32_t div = __lpc43xx_main_clock_mhz / 16 / mhz;
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writel(BASE_CLK_SEL(__lpc43xx_main_clock_sel), BASE_UART_CLK);
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writel(LCR_DLAB, UART_BASE + REG_LCR);
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writel(div & 0xFF, UART_BASE + REG_DLL);
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writel((div >> 8) & 0xFF, UART_BASE + REG_DLM);
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writel(LCR_WLS_8 | LCR_SBS_1, UART_BASE + REG_LCR);
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writel(FCR_FIFOEN | FCR_RX_TRIG_1 | FCR_DMAMODE, UART_BASE + REG_FCR);
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}
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}
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unsigned swo_set_clock(unsigned khz) {
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if (khz >= 12000) {
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khz = 12000;
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} else if (khz >= 8000) {
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khz = 8000;
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} else if (khz >= 6000) {
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khz = 6000;
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} else if (khz >= 4000) {
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khz = 4000;
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} else if (khz >= 3000) {
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khz = 3000;
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} else if (khz >= 2000) {
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khz = 2000;
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} else {
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khz = 1000;
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}
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swo_config(khz * 1000);
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return khz;
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}
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