583 lines
17 KiB
C
583 lines
17 KiB
C
/*
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* Copyright (c) 2014 Christopher Anderson
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <lib/console.h>
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#include <debug.h>
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#include <list.h>
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#include <err.h>
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#include <errno.h>
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#include <reg.h>
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#include <endian.h>
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#include <stdio.h>
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#include <string.h>
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#include <malloc.h>
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#include <trace.h>
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#include <bits.h>
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#include <pow2.h>
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#include <sys/types.h>
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#include <lib/cbuf.h>
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#include <kernel/timer.h>
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#include <kernel/thread.h>
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#include <kernel/vm.h>
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#include <kernel/spinlock.h>
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#include <kernel/debug.h>
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#include <platform/interrupts.h>
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#include <platform/debug.h>
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#include <platform/gem.h>
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#include <platform.h>
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#include <kernel/event.h>
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#include <kernel/semaphore.h>
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#include <lib/pktbuf.h>
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#define LOCAL_TRACE 0
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#define GEM_RX_BUF_CNT 32
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#define GEM_TX_BUF_CNT 32
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#define GEM_RX_BUF_SIZE 1536
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#define GEM_TX_BUF_SIZE 1536
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static spin_lock_t lock = SPIN_LOCK_INITIAL_VALUE;
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struct gem_desc {
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uint32_t addr;
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uint32_t ctrl;
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};
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/* Quick overview:
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* RX:
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* rx_tbl contains rx descriptors. A pktbuf is allocated for each of these and a descriptor
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* entry in the table points to a buffer in the pktbuf. rx_tbl[X]'s pktbuf is stored in rx_pbufs[X]
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*
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* TX:
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* The current position to write new tx descriptors to is maintained by gem.tx_head. As frames are
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* queued in tx_tbl their pktbufs are stored in the list queued_pbufs. As frame transmission is
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* completed these pktbufs are released back to the pool by the interrupt handler for TX_COMPLETE
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*/
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struct gem_descs {
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struct gem_desc rx_tbl[GEM_RX_BUF_CNT];
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struct gem_desc tx_tbl[GEM_TX_BUF_CNT];
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};
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struct gem_state {
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volatile struct gem_regs *regs;
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struct gem_descs *descs;
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paddr_t descs_phys;
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unsigned int tx_head;
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unsigned int tx_tail;
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unsigned int tx_count;
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struct list_node tx_queue;
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struct list_node queued_pbufs;
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gem_cb_t rx_callback;
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event_t rx_pending;
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event_t tx_complete;
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bool debug_rx;
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pktbuf_t *rx_pbufs[GEM_RX_BUF_CNT];
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};
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struct gem_state gem;
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static void debug_rx_handler(pktbuf_t *p)
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{
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static uint32_t pkt = 0;
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printf("[%10u] packet %u, %zu bytes:\n", (uint32_t)current_time(), ++pkt, p->dlen);
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hexdump8(p->data, p->dlen);
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putchar('\n');
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}
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static int free_completed_pbuf_frames(void) {
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int ret = 0;
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gem.regs->tx_status = gem.regs->tx_status;
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while (gem.tx_count > 0 &&
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(gem.descs->tx_tbl[gem.tx_tail].ctrl & TX_DESC_USED)) {
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bool eof;
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do {
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pktbuf_t *p = list_remove_head_type(&gem.queued_pbufs, pktbuf_t, list);
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DEBUG_ASSERT(p);
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eof = p->eof;
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ret += pktbuf_free(p, false);
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} while (!eof);
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gem.tx_tail = (gem.tx_tail + 1) % GEM_TX_BUF_CNT;
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gem.tx_count--;
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}
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return ret;
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}
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void queue_pkts_in_tx_tbl(void) {
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pktbuf_t *p;
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unsigned int cur_pos;
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if (list_is_empty(&gem.tx_queue)) {
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return;
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}
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// XXX handle multi part buffers
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/* Queue packets in the descriptor table until we're either out of space in the table
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* or out of packets in our tx queue. Any packets left will remain in the list and be
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* processed the next time available */
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while (gem.tx_count < GEM_TX_BUF_CNT &&
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((p = list_remove_head_type(&gem.tx_queue, pktbuf_t, list)) != NULL)) {
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cur_pos = gem.tx_head;
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uint32_t addr = pktbuf_data_phys(p);
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uint32_t ctrl = gem.descs->tx_tbl[cur_pos].ctrl & TX_DESC_WRAP; /* protect the wrap bit */
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ctrl |= TX_BUF_LEN(p->dlen);
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DEBUG_ASSERT(p->eof); // a multi part buffer would have caused a race condition w/hardware
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if (p->eof) {
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ctrl |= TX_LAST_BUF;
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}
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/* fill in the descriptor, control word last (in case hardware is racing us) */
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gem.descs->tx_tbl[cur_pos].addr = addr;
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gem.descs->tx_tbl[cur_pos].ctrl = ctrl;
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gem.tx_head = (gem.tx_head + 1) % GEM_TX_BUF_CNT;
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gem.tx_count++;
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list_add_tail(&gem.queued_pbufs, &p->list);
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}
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DMB;
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gem.regs->net_ctrl |= NET_CTRL_START_TX;
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}
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int gem_send_raw_pkt(struct pktbuf *p)
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{
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status_t ret = NO_ERROR;
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if (!p || !p->dlen) {
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ret = -1;
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goto err;
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}
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/* make sure the output buffer is fully written to memory before
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* placing on the outgoing list. */
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// XXX handle multi part buffers
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arch_clean_cache_range((vaddr_t)p->data, p->dlen);
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spin_lock_saved_state_t irqstate;
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spin_lock_irqsave(&lock, irqstate);
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list_add_tail(&gem.tx_queue, &p->list);
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queue_pkts_in_tx_tbl();
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spin_unlock_irqrestore(&lock, irqstate);
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err:
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return ret;
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}
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enum handler_return gem_int_handler(void *arg) {
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uint32_t intr_status;
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bool resched = false;
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intr_status = gem.regs->intr_status;
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spin_lock(&lock);
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while (intr_status) {
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// clear any pending status
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gem.regs->intr_status = intr_status;
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// Received an RX complete
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if (intr_status & INTR_RX_COMPLETE) {
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event_signal(&gem.rx_pending, false);
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gem.regs->rx_status |= INTR_RX_COMPLETE;
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resched = true;
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}
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if (intr_status & INTR_RX_USED_READ) {
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for (int i = 0; i < GEM_RX_BUF_CNT; i++) {
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gem.descs->rx_tbl[i].addr &= ~RX_DESC_USED;
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}
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gem.regs->rx_status &= ~RX_STATUS_BUFFER_NOT_AVAIL;
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gem.regs->net_ctrl &= ~NET_CTRL_RX_EN;
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gem.regs->net_ctrl |= NET_CTRL_RX_EN;
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printf("GEM overflow, dumping pending packets\n");
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}
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if (intr_status & INTR_TX_CORRUPT) {
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printf("tx ahb error!\n");
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if (free_completed_pbuf_frames() > 0) {
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resched = true;
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}
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}
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/* A frame has been completed so we can clean up ownership of its buffers */
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if (intr_status & INTR_TX_COMPLETE) {
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if (free_completed_pbuf_frames() > 0) {
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resched = true;
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}
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}
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/* The controller has processed packets until it hit a buffer owned by the driver */
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if (intr_status & INTR_TX_USED_READ) {
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queue_pkts_in_tx_tbl();
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gem.regs->tx_status |= TX_STATUS_USED_READ;
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}
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/* see if we have any more */
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intr_status = gem.regs->intr_status;
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}
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spin_unlock(&lock);
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return (resched) ? INT_RESCHEDULE : INT_NO_RESCHEDULE;
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}
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static bool wait_for_phy_idle(void)
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{
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int iters = 1000;
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while (iters && !(gem.regs->net_status & NET_STATUS_PHY_MGMT_IDLE)) {
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iters--;
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}
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if (iters == 0) {
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return false;
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}
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return true;
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}
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static bool gem_phy_init(void) {
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return wait_for_phy_idle();
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}
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static status_t gem_cfg_buffer_descs(void)
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{
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/* Take pktbufs from the allocated target pool and assign them to the gem RX
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* descriptor table */
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for (unsigned int n = 0; n < GEM_RX_BUF_CNT; n++) {
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pktbuf_t *p = pktbuf_alloc();
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if (!p) {
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return -1;
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}
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gem.rx_pbufs[n] = p;
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gem.descs->rx_tbl[n].addr = (uintptr_t) p->phys_base;
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gem.descs->rx_tbl[n].ctrl = 0;
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}
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/* Claim ownership of TX descriptors for the driver */
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for (unsigned i = 0; i < GEM_TX_BUF_CNT; i++) {
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gem.descs->tx_tbl[i].addr = 0;
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gem.descs->tx_tbl[i].ctrl = TX_DESC_USED;
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}
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/* Both set of descriptors need wrap bits set at the end of their tables*/
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gem.descs->rx_tbl[GEM_RX_BUF_CNT-1].addr |= RX_DESC_WRAP;
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gem.descs->tx_tbl[GEM_TX_BUF_CNT-1].ctrl |= TX_DESC_WRAP;
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/* Point the controller at the offset into state's physical location for RX descs */
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gem.regs->rx_qbar = ((uintptr_t)&gem.descs->rx_tbl[0] - (uintptr_t)gem.descs) + gem.descs_phys;
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gem.regs->tx_qbar = ((uintptr_t)&gem.descs->tx_tbl[0] - (uintptr_t)gem.descs) + gem.descs_phys;
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return NO_ERROR;
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}
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static void gem_cfg_ints(void)
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{
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uint32_t gem_base = (uintptr_t)gem.regs;
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if (gem_base == GEM0_BASE) {
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register_int_handler(ETH0_INT, gem_int_handler, NULL);
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unmask_interrupt(ETH0_INT);
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} else if (gem_base == GEM1_BASE) {
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register_int_handler(ETH1_INT, gem_int_handler, NULL);
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unmask_interrupt(ETH1_INT);
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} else {
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printf("Illegal gem periph base address 0x%08X!\n", gem_base);
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return;
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}
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/* Enable all interrupts */
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gem.regs->intr_en = INTR_RX_COMPLETE | INTR_TX_COMPLETE | INTR_HRESP_NOT_OK | INTR_MGMT_SENT |
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INTR_RX_USED_READ | INTR_TX_CORRUPT | INTR_TX_USED_READ | INTR_RX_OVERRUN;
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}
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int gem_rx_thread(void *arg)
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{
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pktbuf_t *p;
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int bp = 0;
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while (1) {
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event_wait(&gem.rx_pending);
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for (;;) {
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if (gem.descs->rx_tbl[bp].addr & RX_DESC_USED) {
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uint32_t ctrl = gem.descs->rx_tbl[bp].ctrl;
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p = gem.rx_pbufs[bp];
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p->dlen = RX_BUF_LEN(ctrl);
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p->data = p->buffer + 2;
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/* copy the checksum offloading bits */
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p->flags = 0;
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p->flags |= (BITS_SHIFT(ctrl, 23, 22) != 0) ? PKTBUF_FLAG_CKSUM_IP_GOOD : 0;
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p->flags |= (BITS_SHIFT(ctrl, 23, 22) == 1) ? PKTBUF_FLAG_CKSUM_UDP_GOOD : 0;
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p->flags |= (BITS_SHIFT(ctrl, 23, 22) == 2) ? PKTBUF_FLAG_CKSUM_TCP_GOOD : 0;
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/* invalidate any stale cache lines on the receive buffer to ensure
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* the cpu has a fresh copy of incomding data. */
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arch_invalidate_cache_range((vaddr_t)p->data, p->dlen);
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if (unlikely(gem.debug_rx)) {
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debug_rx_handler(p);
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}
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if (likely(gem.rx_callback)) {
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gem.rx_callback(p);
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}
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/* make sure all dirty data is flushed out of the buffer before
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* putting into the receive queue */
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arch_clean_invalidate_cache_range((vaddr_t)p->buffer, PKTBUF_SIZE);
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gem.descs->rx_tbl[bp].addr &= ~RX_DESC_USED;
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gem.descs->rx_tbl[bp].ctrl = 0;
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bp = (bp + 1) % GEM_RX_BUF_CNT;
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} else {
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break;
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}
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}
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}
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return 0;
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}
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void gem_deinit(uintptr_t base)
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{
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/* reset the gem peripheral */
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uint32_t rst_mask;
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if (base == GEM0_BASE) {
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rst_mask = (1<<6) | (1<<4) | (1<<0);
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} else {
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rst_mask = (1<<7) | (1<<5) | (1<<1);
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}
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SLCR->GEM_RST_CTRL |= rst_mask;
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spin(1);
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SLCR->GEM_RST_CTRL &= ~rst_mask;
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/* Clear Network control / status registers */
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gem.regs->net_ctrl |= NET_CTRL_STATCLR;
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gem.regs->rx_status = 0x0F;
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gem.regs->tx_status = 0xFF;
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/* Disable interrupts */
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gem.regs->intr_dis = 0x7FFFEFF;
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/* Empty out the buffer queues */
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gem.regs->rx_qbar = 0;
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gem.regs->tx_qbar = 0;
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}
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/* TODO: Fix signature */
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status_t gem_init(uintptr_t gem_base)
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{
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status_t ret;
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uint32_t reg_val;
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thread_t *rx_thread;
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vaddr_t descs_vaddr;
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paddr_t descs_paddr;
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DEBUG_ASSERT(gem_base == GEM0_BASE || gem_base == GEM1_BASE);
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/* Data structure init */
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event_init(&gem.tx_complete, false, EVENT_FLAG_AUTOUNSIGNAL);
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event_init(&gem.rx_pending, false, EVENT_FLAG_AUTOUNSIGNAL);
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list_initialize(&gem.queued_pbufs);
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list_initialize(&gem.tx_queue);
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/* allocate a block of contiguous memory for the peripheral descriptors */
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if ((ret = vmm_alloc_contiguous(vmm_get_kernel_aspace(), "gem_desc",
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sizeof(*gem.descs), (void **)&descs_vaddr, 0, 0, ARCH_MMU_FLAG_UNCACHED_DEVICE)) < 0) {
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return ret;
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}
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if ((ret = arch_mmu_query(descs_vaddr, &descs_paddr, NULL)) < 0) {
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return ret;
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}
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/* tx/rx descriptor tables and memory mapped registers */
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gem.descs = (void *)descs_vaddr;
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gem.descs_phys = descs_paddr;
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gem.regs = (struct gem_regs *)gem_base;
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/* rx background thread */
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rx_thread = thread_create("gem_rx", gem_rx_thread, NULL, HIGH_PRIORITY, DEFAULT_STACK_SIZE);
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thread_resume(rx_thread);
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/* Bring whatever existing configuration is up down so we can do it cleanly */
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gem_deinit(gem_base);
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gem_cfg_buffer_descs();
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/* Self explanatory configuration for the gige */
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reg_val = NET_CFG_FULL_DUPLEX;
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reg_val |= NET_CFG_GIGE_EN;
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reg_val |= NET_CFG_SPEED_100;
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reg_val |= NET_CFG_RX_CHKSUM_OFFLD_EN;
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reg_val |= NET_CFG_FCS_REMOVE;
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reg_val |= NET_CFG_MDC_CLK_DIV(0x7);
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reg_val |= NET_CFG_RX_BUF_OFFSET(2);
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gem.regs->net_cfg = reg_val;
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/* Set DMA to 1600 byte rx buffer, 8KB addr space for rx, 4KB addr space for tx,
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* hw checksumming, little endian, and use INCR16 ahb bursts
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*/
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reg_val = DMA_CFG_AHB_MEM_RX_BUF_SIZE(0x19);
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reg_val |= DMA_CFG_RX_PKTBUF_MEMSZ_SEL(0x3);
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reg_val |= DMA_CFG_TX_PKTBUF_MEMSZ_SEL;
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reg_val |= DMA_CFG_CSUM_GEN_OFFLOAD_EN;
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reg_val |= DMA_CFG_AHB_FIXED_BURST_LEN(0x10);
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gem.regs->dma_cfg = reg_val;
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/* Enable VREF from GPIOB */
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SLCR_REG(GPIOB_CTRL) = 0x1;
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ret = gem_phy_init();
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if (!ret) {
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printf("Phy not idle, aborting!\n");
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return ret;
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}
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gem_cfg_ints();
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reg_val = NET_CTRL_MD_EN;
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reg_val |= NET_CTRL_RX_EN;
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reg_val |= NET_CTRL_TX_EN;
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gem.regs->net_ctrl = reg_val;
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return NO_ERROR;
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}
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void gem_disable(void)
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{
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/* disable all the interrupts */
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gem.regs->intr_en = 0;
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mask_interrupt(ETH0_INT);
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/* stop tx and rx */
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gem.regs->net_ctrl = 0;
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}
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void gem_set_callback(gem_cb_t rx)
|
|
{
|
|
gem.rx_callback = rx;
|
|
}
|
|
|
|
void gem_set_macaddr(uint8_t mac[6]) {
|
|
uint32_t en = gem.regs->net_ctrl &= NET_CTRL_RX_EN | NET_CTRL_TX_EN;
|
|
|
|
if (en) {
|
|
gem.regs->net_ctrl &= ~(en);
|
|
}
|
|
|
|
/* _top register must be written after _bot register */
|
|
gem.regs->spec_addr1_bot = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
|
|
gem.regs->spec_addr1_top = (mac[5] << 8) | mac[4];
|
|
|
|
if (en) {
|
|
gem.regs->net_ctrl |= en;
|
|
}
|
|
}
|
|
|
|
|
|
/* Debug console commands */
|
|
static int cmd_gem(int argc, const cmd_args *argv)
|
|
{
|
|
static uint32_t frames_rx = 0, frames_tx = 0;
|
|
|
|
if (argc == 1) {
|
|
printf("gem [d]ebug: enable RX debug output\n");
|
|
printf("gem [r]aw <iter> <length>: Send <iter> raw mac packet for testing\n");
|
|
printf("gem [s]tatus: print driver status\n");
|
|
} else if (argv[1].str[0] == 'r') {
|
|
pktbuf_t *p;
|
|
int iter;
|
|
if (argc < 4) {
|
|
return 0;
|
|
}
|
|
|
|
if ((p = pktbuf_alloc()) == NULL) {
|
|
printf("out of buffers\n");
|
|
}
|
|
|
|
iter = argv[2].u;
|
|
p->dlen = argv[3].u;
|
|
while (iter--) {
|
|
memset(p->data, iter, 12);
|
|
gem_send_raw_pkt(p);
|
|
}
|
|
} else if (argv[1].str[0] == 's') {
|
|
uint32_t mac_top = gem.regs->spec_addr1_top;
|
|
uint32_t mac_bot = gem.regs->spec_addr1_bot;
|
|
printf("mac addr: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
|
mac_top >> 8, mac_top & 0xFF, mac_bot >> 24, (mac_bot >> 16) & 0xFF,
|
|
(mac_bot >> 8) & 0xFF, mac_bot & 0xFF);
|
|
uint32_t rx_used = 0, tx_used = 0;
|
|
for (int i = 0; i < GEM_RX_BUF_CNT; i++) {
|
|
rx_used += !!(gem.descs->rx_tbl[i].addr & RX_DESC_USED);
|
|
}
|
|
|
|
for (int i = 0; i < GEM_TX_BUF_CNT; i++) {
|
|
tx_used += !!(gem.descs->tx_tbl[i].ctrl & TX_DESC_USED);
|
|
}
|
|
|
|
frames_tx += gem.regs->frames_tx;
|
|
frames_rx += gem.regs->frames_rx;
|
|
printf("rx usage: %u/%u, tx usage %u/%u\n",
|
|
rx_used, GEM_RX_BUF_CNT, tx_used, GEM_TX_BUF_CNT);
|
|
printf("frames rx: %u, frames tx: %u\n",
|
|
frames_rx, frames_tx);
|
|
#if 0
|
|
printf("rx descriptors:\n");
|
|
hexdump(gem.descs->rx_tbl, GEM_RX_BUF_CNT * sizeof(struct gem_desc));
|
|
printf("tx descriptors:\n");
|
|
hexdump(gem.descs->tx_tbl, GEM_TX_BUF_CNT * sizeof(struct gem_desc));
|
|
printf("tx head %u tail %u (%p %p)\n", gem.tx_head, gem.tx_tail,
|
|
&gem.descs->tx_tbl[gem.tx_head], &gem.descs->tx_tbl[gem.tx_tail]);
|
|
#endif
|
|
} else if (argv[1].str[0] == 'd') {
|
|
gem.debug_rx = !gem.debug_rx;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
STATIC_COMMAND_START
|
|
STATIC_COMMAND("gem", "ZYNQ GEM commands", &cmd_gem)
|
|
STATIC_COMMAND_END(gem);
|