86267ca23c
To work properly with some hypervisors on various architectures (ARM, ARM64, x86), add global routines to allow access to MMIO registers via architecturally defined accessors. Add accessors for ARM, ARM64, and x86-32/64. Have the other arches default to just using whatever the compiler emits. Will need to generally move things off the legacy REG*() accessors since they're really not safe going forward with what compilers emit.
50 lines
1.6 KiB
C
50 lines
1.6 KiB
C
/*
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* Copyright (c) 2024 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#include <stdint.h>
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// Accessor routines for this architecture, used in include/reg.h
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//
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// Simple load/store instructions with a basic addressing mode of either
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// [reg], [reg, #imm] or [reg, reg], with no writeback are guaranteed to be
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// fully decoded into ESR_EL2 for hypervisor assist.
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#define ARCH_MMIO_READ_WRITE_OVERRIDE 1
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#define _ARCH_MMIO_READ8(addr) ({ \
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uint8_t val; \
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__asm__ volatile("ldrb %w0, %1" : "=r"(val) : "m"(*(addr)) : "memory"); \
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val; \
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})
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#define _ARCH_MMIO_READ16(addr) ({ \
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uint16_t val; \
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__asm__ volatile("ldrh %w0, %1" : "=r"(val) : "m"(*(addr)) : "memory"); \
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val; \
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})
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#define _ARCH_MMIO_READ32(addr) ({ \
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uint32_t val; \
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__asm__ volatile("ldr %w0, %1" : "=r"(val) : "m"(*(addr)) : "memory"); \
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val; \
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})
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#define _ARCH_MMIO_READ64(addr) ({ \
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uint64_t val; \
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__asm__ volatile("ldr %0, %1" : "=r"(val) : "m"(*(addr)) : "memory"); \
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val; \
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})
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#define _ARCH_MMIO_WRITE8(addr, val) \
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__asm__ volatile("strb %w1, %0" : "=m"(*(addr)) : "r"(val) : "memory")
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#define _ARCH_MMIO_WRITE16(addr, val) \
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__asm__ volatile("strh %w1, %0" : "=m"(*(addr)): "r"(val) : "memory")
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#define _ARCH_MMIO_WRITE32(addr, val) \
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__asm__ volatile("str %w1, %0" : "=m"(*(addr)) : "r"(val) : "memory")
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#define _ARCH_MMIO_WRITE64(addr, val) \
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__asm__ volatile("str %1, %0" : "=m"(*(addr)) : "r"(val) : "memory")
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